With multi patterning being the method of choice for pushing technology further down the shrink roadmap, new design weak points are emerging that have multi-layer components and are difficult to find and to define. On the other hand, advanced OPC methodologies like retargeting and recentering help alleviate many of the occurrences, leaving only a few locations that are critical and need to be dealt with in design. State of the art in-design weak point auto fixing is usually done by identifying a weak point by a pattern match, and providing the router either a “safe” alternative configuration or tell it to reroute locally, also called rip-and-reroute. The dilemma for developing pattern matching decks that are used in place and route tools is that one cannot be too specific in the pattern definition as there will be escapes that can possibly cause problems in the fab. Having a more general pattern definition will prevent escapes, but will flag many locations that don’t really require fixing. As a consequence, this more general pattern definition may bog down the place and route tool and can actually result in area bloat if too many rip-and-reroute areas are identified. We have come up with a patented flow that allows very specific weak point detection with a low escape rate. The flow starts with a generic pattern definition of the fail mode, but reduces the number of occurrences by identifying safe configurations. Usually, the pattern extent of the safe configuration is larger than the initial generic pattern, and may contain more layers. Any known safe configuration is added to a “good pattern” database which is then subtracted from the initial pattern match. Thus, the number of design locations that need to be auto fixed is kept at a minimum. As the technology matures, more safe patterns are found and added to the database, thus reducing the amount of auto fixing required.
This paper presents a methodology to optimize standard cells and other small IP for manufacturability. The optimization is based on an evolutionary machine learning algorithm. This algorithm creates variants of a starting cell by randomly selecting and moving edges, and selects the best variant based on a scoring methodology for the next set of iterations. The opportunity for such an algorithm arises from the complexity of advanced node design rules, where multiple rules compete and have to be optimized simultaneously across multiple mask layers. Doing this process manually is a lengthy and highly iterative process and most often leaves DFM opportunities on the table. The selector in the algorithm is a combination of MAS/DRC rule-based checks, and a holistic multi-layer lithographic process window metric. Specifically library standard cells can be optimized for DFM scores and printability within a very short time frame.
Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.
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