Light-emitting diode (LED) photonics is a rapidly growing field that has applications in various domains, such as communication, lighting, display, and sensing. However, the fabrication and characterization of LED photonic devices pose several challenges that need to be addressed. Compared to the silicon semiconductor industry, LED devices are based on exotic substrates, such as sapphire (AlO), silicon carbide (SiC) and gallium arsenide (GaAs). One of the challenges in semiconductor process integration development and production control is checking the process quality through characterizing and analyzing defects at different process steps. Typically, wafers at different process steps are sent to the failure analysis laboratory (FA lab) for detailed analysis by transmission electron microscope (TEM), energydispersive X-ray spectroscopy (EDX), cross scanning electron microscope (XSEM), or gallium focus ion beam (GaFIB). These methods are destructive, slow, and expensive. As a result, having a non-destructive, fast, and low-cost method for full-wafer analysis can help speed up the integration cycle and improve process control and yield. This paper is a collaboration between ams-OSRAM international GmbH and Applied Materials Inc. The paper describes the benefits of inline Xenon Plasma FIB (XePFIB) and SEM in the fab for improving the cycle time of root cause analysis and process integration development. It explains the methods that are used to solve the problems of handling and analyzing special substrates, like transparent sapphire wafers in semiconductor manufacturing for LED and photonic products. Specifically, the paper describes the methodologies that are used to optimize the SEM image resolution and XePFIB cross-section quality by reducing the charging effects of the sapphire dielectric substrate.
KEYWORDS: Critical dimension metrology, Semiconducting wafers, Process control, 3D metrology, Back end of line, Front end of line, Image quality, 3D image processing, Xenon, Plasma
In recent years semiconductor manufacturers have increasingly employed deep through-silicon via (TSV) at the front end of line (FEOL) process steps, combined with using an increased number of multilevel, three-dimensional (3D) layers with different material stack at the back end of line (BEOL) process steps. This increased usage results in enhanced requirements for 3D feature characterization during the process development steps, as well as with monitoring and failure analysis during production.
Traditionally, deep TSV features during the FEOL are analyzed by cleaving (breaking) the wafers and observing the cross section. At the BEOL, focused ion beam (FIB) cross section and etch back or chemical mechanical polishing (CMP) of layer-by-layer are used to characterize the 3D multilevel layers. Both methods result in a slow turnaround time (TAT), but most importantly, cross section analysis only gives two-dimensional (2D) information about 3D multilevel structure and can miss abnormalities. Etch back or CMP has relatively low quality, accuracy, and repeatability and results in full wafer scrap.
Inline Xe plasma FIB (PFIB) has become an important tool for 3D feature characterization and failure analysis in the chip manufacturing production line. Layer-by-layer excavation (also known as delayering) of a specific site provides enhanced metrology and reconstruction of complete 3D features. Thus, manufacturers can identify process abnormalities of the complete structure. Moreover, inline delayering, combined with cross sectioning of specific sites, enhances the TAT. The wafer can return to production for further analysis, and manufacturers can study the effects on different steps.
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