We present the performance of 4-channel × 25 Gb/s all-silicon photonic receivers based on hybrid-integrated vertical Ge-on-bulk-silicon photodetectors with 65nm bulk CMOS front-end circuits, characterized over 100 Gb/s. The sensitivity of a single-channel Ge photoreceiver module at a BER = 10-12 was measured -11 dBm at 25 Gb/s, whereas, the measured sensitivity of a 4-ch Ge photoreceiver was -10.06 ~ -10.9 dBm for 25Gb/s operation of each channel, and further improvement is in progress. For comparison, we will also present the performance of a 4-ch × 25 Gb/s photoreceiver module, where commercial InP HBT-based front-end circuits is used, characterized up to 100 Gb/s.
We present high performance vertical-illumination type Ge-on-Si avalanche photodetectors and photoreceiver modules operating up to 25 Gb/s. The Ge avalanche photodetectors were grown on a bulk-silicon wafer by RPCVD, and fabricated with CMOS-compatible process. The fabricated devices show a -3dB bandwidth greater than 13 GHz at operational biases (gain> 20) for λ ~ 1550 nm. The measured maximum gain-bandwidth (GB) product is ~ 493 GHz. Two types of Ge-on-Si APD receiver modules exhibit high sensitivities of better than –20.7 dBm for a 25 Gb/s operation at a BER = 10-12 and λ ~ 1310 nm, and –27.75 dBm for a 10 Gb/s operation at a BER = 10-12 and λ ~ 1550nm, respectively.
We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.
Advancement of silicon photonics technology can offer a new dimension in data communications with un-precedent bandwidth. Increasing the integration level in the silicon photonics is required to develop compact high-performance chip-level optical interconnects for future systems. Especially, monolithic integration of light source on a silicon wafer is important for future silicon photonic integrated circuits, since realizing a compact on-chip light source on a silicon wafer is a serious issue which impedes practical implementation of the silicon photonic interconnects. At present, due to the lack of a practical light source based on Group IV elements, flip chip-bonded or packaged lasers based on III–V semiconductor are usually being used as external light sources, to feed silicon modulators on SOI wafers to complete a photonic transmitter, except the reported silicon hybrid lasers monolithic-integrated on SOI wafers. To overcome above problem, we have proposed a compact on-chip light source, the directly monolithic-integrated VCSEL on a bulk silicon wafer (VCSEL-on-Si), based on the transplanted epitaxial film by substrate lift-off process and following device-fabrication on the bulk Si wafer. This can offer practical low-power-consumption light sources integrated on a silicon wafer, which can provide a complete chip-level I/O set when combined with monolithic-integrated vertical-illumination Ge-on-Si photodetectors on the same silicon wafer. In this work, we report the characterization of direct-modulation VCSELs-on-Si for λ ~850 nm with CW optical output power > ~2 mW and the threshold current < ~3 mA, over 10 Gb/s operations. We also discuss about the thermal characteristics of the VCSELs-on-Si.
We report a 40 Gb/s photoreceiver based on vertical-illumination type Ge-on-Si photodetectors and a silica-based AWG
demultiplexer by employing 4-channel CWDM. The 60um-diameter Ge-on-Si photodetector arrays, grown on a bulk
silicon wafer by RPCVD and fabricated with CMOS-compatible process, have ~0.9 A/W responsivity with 13 GHz
bandwidth at λ ~ 1330nm. Ge-on-Si photodetector arrays are hybrid-integrated with TIA/LAs and directly-coupled to the
AWG. The low-cost FPCB-package based photoreceiver module shows 10.3 Gb/s × 4-channel interconnection with -11
~ -12.2 dBm sensitivity at a BER = 10-12.
Based on either a SOI wafer or a bulk-silicon wafer, we discuss silicon photonic devices and integrations for chip-level
optical interconnects. We present the low-voltage silicon PICs on a SOI wafer, where Si modulators and Ge-on-Si
photodetectors are monolithically-integrated for intra-chip or inter-chip interconnects over 40 Gb/s. For future chip-level
integration, the 50 Gb/s small-sized depletion-type MZ modulator with the vertically-dipped PN-depletion-junction
(VDJ) is also presented. We report vertical-illumination-type Ge photodetectors on bulk-silicon wafers, with high
performances up to 50 Gb/s. We present the bulk-silicon platform for practical implementation of chip-level
interconnects, and the performance of the photonic transceiver silicon chip.
We report the silicon photonic receivers based on the hybrid-integrated vertical-illumination-type germanium-on-silicon
photodetector and CMOS amplifier circuit, for optical interconnects. The high-speed vertical-illumination-type Ge-on-Si
photodetector is defined on a bulk-silicon wafer, and the CMOS amplifier chip was designed with 65nm ground rule.
The PCB-packaged 4 channel 25 Gb/s photoreceiver exhibits a resposivity of 0.68A/W. The sensitivity measured at a
BER of 10−12 is -8.3 dBm and -2.4dBm for 25Gb/s and 32Gb/s, respectively. The energy efficiency is 2.19 pJ/bit at 25
Gb/s. The single-channel butterfly-packaged photoreceiver exhibits the sensitivity of -11dBm for 25 Gb/s at a BER of
10−12. The energy efficiency is 2.67 pJ/bit at 25 Gb/s.
We investigate the improvement of an insertion loss in silicon arrayed waveguide grating (AWG), by analyzing the
multimode generation due to the field-mismatching effect. 8 channel silicon AWGs on a 6” SOI wafer are fabricated
with an ultra-shallow etching structure and various aperture size of arrayed WGs. Our experimental results demonstrate
the improved insertion loss and crosstalk characteristics. The fabricated AWG shows an insertion loss less than 1 dB
with a crosstalk of -23.2 ~ -25.6 dB, exhibiting ~2.5 dB improvement of insertion loss and ~5 dB improvement of
crosstalk, compared to our reported result.
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