Mr. Paul J. Newman Profile

Paul J. Newman

at Griffith Univ

SPIE Involvement:

Author

Publications (1)

Proceedings Article | 16 February 2005 Paper

A low-cost CMOS neurological sensor array

Paul Newman, Peter Lisner, Y. Yeow, Peng Choy, Nick Lavidis

Proceedings Volume 5651, (2005) https://doi.org/10.1117/12.582187

KEYWORDS: Sensors, Amplifiers, Nerve, Metals, Quantization, CMOS sensors, Analog electronics, Temporal resolution, Tissues, Field effect transistors

Read Abstract +

Current methods used to study neural communication have not been able to achieve both good spatial and temporal resolution of recordings. There are two ways to record synaptic potentials from nerve endings: recordings using single or dual intracellular or extra cellular metal electrodes give good temporal resolution but poor spatial resolution, and recording activity with fluorescent dyes gives good spatial resolution but poor temporal resolution. Such medical research activity in the area of neurological signal detection has thus identified a requirement for the design of a CMOS circuit that contains an array of independent sensors. As both spatial and temporal distribution of acquired data is required in this application, the circuit must be capable of continuous measurement of synaptic potentials from an array of points on a tissue sample, with a 10 μm separation between sensor points. The major requirement for the circuit is that it is capable of sensing synaptic potentials of the order of several mV, with a resolution of 0.05 mV. For data recording purposes, the circuit must amplify these synaptic potentials and digitise them together with their locations in the sensor array. Finally, the circuit must be biologically inert, to avoid specimen deterioration. This paper presents the design of a prototype single-chip circuit, which provides a 6 x 3 array of independent synaptic potential sensors. The signal from each of the sensors is amplified and time-multiplexed into an on-chip A/D converter. The circuit provides an 8-bit synaptic potential value, together with an 8-bit field containing array location and trigger signals suitable for external data acquisition instrumentation. Our test circuit is implemented in a low-cost 0.5 um, 5 V CMOS process. The fabricated die is mounted in a standard 40 pin DIP ceramic package, with no lid to allow direct contact of the die surface with the tissue sample. The only post-processing step required for these packages is to encapsulate the exposed bond wires to ensure that the device is biologically inert. No further processing of the silicon die is required. Both the circuit design and the chip performance will be presented in the seminar.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years