Base on the special characters of off-axis spherical and three-axis ion beam figuring (IBF) system, a method of obtaining the removal function depending on incidence angles are introduced and the curve be indicated. Keeping the fabrication coordinate coincident to the optical coordinate can avoid the transformation of interferometry map, which could introduce the distortion error. By analyzing of the process of polishing the 562mm×290mm off-axis mirror, the polishing experimentation has been carried out on the IBF2000 system developed by NTG. After two iterations and 37.2 hours polishing time, the RMS value of surface accuracy is from 0.033λ to 0.016λ, and the mid-spatial error mitigated dramatically. The experimentation indicates that using the non-contacting polishing feature of IBF with reasonable optimizing process, the surface accuracy and the mid-spatial error can be improved simultaneously.
For the existing monocular vision methods of pose (or position and orientation) measurement based on the Perspective-n-Point problem, camera calibrations and image corrections are complicated and difficult due to the lens distortion. Additionally, as their theoretical models, the pinhole imaging model and the collinear equation only offer an ideal approximation for the imaging process of the area array camera. Thus, the measurement possesses inevitable systematic errors. To avoid these problems, a new pose measuring method is proposed, which replaces the area array camera and its collinear equation with two line array cameras and their incident light plane equations, respectively. For these two line array cameras, their mechanical assembly requirements and calibration steps are also analysed; they only require that the two optical centre lines of their cylindrical lenses be perpendicular to each other, and only need to be calibrated for the relationship between the coordinate of the image line and the incident angle of the incident light plane. The experiment results of P4P pose measurement with the proposed method showed only significant random errors and no significant systematic error, confirming that this method has eliminated the problems caused by the image distortion and model approximation.
Link Capacity Adjustment Scheme (LCAS) is a protocol to provide hitless bandwidth adjustment of virtual concatenated (VCAT) signal under the control of network management system (NMS). It has much larger flexibility to dynamically assign resources and becomes an important feature for multi-service transport platform (MSTP) systems. However, the scheme is a two-way handshake signalling with status messages exchanged continuously, which can hardly be implemented within a single chip. Aiming at an easier implementation in ASIC, we revise the LCAS protocol to have a shorter handshaking procedure by adding MST bits in the reserved K4 bits and remove the complex mappings between TU12s and theirs SQs. Simulation results show that the revised LCAS shortens the period of handshaking procedure and synthesis results show that the size of logic is greatly reduced. We believe the new scheme will be accepted and applied in future.
We design a novel tunable interchannel dispersion-slope compensator using a single broad-band nonchannelized sampled fiber Bragg grating (FBG) with chirp in the sampling period. Tunability of the dispersion-slope can be achieved by stressing or heating the grating uniformly, which has a third-order time-delay variation with wavelength, thereby causing a second-order variation in dispersion. By using the equivalent-chirp method, i.e. by chirping the sampling function, we get the time-delay within -1st order Fourier reflection band and consequently realize dispersion-slope compensator.
The speed of high-performance switches and routers is often limited by the bandwidth of commercially available memories. Meanwhile, the rapid growth in network bandwidth accompanied by the slowly increasing memory speed makes the problem even harder over time. There are, in fact, several techniques to build faster memories. However, some are based on the ideas from computer systems, such as parallelism, interleaving and banking, which can hardly be applied directly to packet buffering, while the others like hybrid SRAM-DRAM packet buffers are restricted by the speed of SRAM and inapplicable as the link rate exceeds the speed of SRAM. Motivated by increasing the throughput of packet buffers with only common memory arrays, we present one particular packet buffer architecture called Tri-Stage Memory Array (TSMA) that can speed up the packet buffering and retrieving processes to an arbitrary high speed theoretically. To replenish TSMA, a memory management algorithm called Most Urgent Queue First (MUQF) is also described and analyzed. It is proved that TSMA architecture coupled with MUQF algorithm can guarantee a bounded delay for each packet under any traffic arrival pattern or scheduling algorithm. Moreover, we provide an alternative architecture of TSMA to achieve simple implementation.
KEYWORDS: Networks, Virtual colonoscopy, Error control coding, Field programmable gate arrays, Transmitters, Data transmission, Standards development, Time division multiplexing, Local area networks, Receivers
Ethernet over SDH/SONET (EOS), which connects different Ethernets through the existing SDH/SONET infrastructure, is a promising data transmission technology in today’s networks, for it successfully combines the simplicity and affordability of Ethernet with the resilience and scalability of SDH/SONET. Virtual Concatenation (VCAT) is one of the key technologies in EOS, which provides the capability to transmit and receive over several noncontiguous parallel Virtual Container (VC) fragments as a single flow and drastically improves efficiency of over 33 percent against standard concatenations. Link capacity adjustment scheme (LCAS) over VCAT signaling scheme further enhances VCAT to tune bandwidth dynamically at the requests of network management system without disturbing the existing traffic. In addition, the scheme will automatically decrease the capacity if some member of VCAT experiences a failure in the network, and increase the capacity when the network fault is repaired. In this paper, our design of LCAS over VCAT within an EOS chip is provided, which supports four Virtual Concatenation Groups (VCG) to adjust their bandwidth simultaneously. The block diagrams of the total design for LCAS over VCAT are also provided and several open problems that we encountered during implementation and their corresponding solutions are discussed in focus. Thoroughly functional simulations and FPGA verifications have been done to the design to prove its validity. Finally, we have the design synthesized with Synopsys’s Design Compiler, which reveals that the whole design is realizable in ASICs.
KEYWORDS: Digital watermarking, Local area networks, Switches, Electronics engineering, Sensors, Green fluorescent protein, Computer simulations, Computing systems, Data transmission, Control systems
As is known, Ethernet has gained great popularity in LAN (local area network). Meanwhile, SDH/SONET is the backbone of today’s communication networks. Then, how to exchange information between Ethernets located in different regions over SDH/SONET is becoming a hotspot. This paper provides a single chip solution of Ethernet transmission over SDH/SONET (EOS), which supports up to thirty-two 10/100Mbit/s Ethernet ports or four 1000Mbit/s Ethernet ports over 2.5Gbit/s SDH/SONET. On designing of this EOS chip, we also present a packet loss policy called SDP (Selective Dropping Policy) to perform flow control, which can actively select packets to drop as the packet buffer overflows. Up to now, we have developed two policies of SDP: LPF (Longest Packet First) and LSPF (Least Significant Packet First). Simulation results show that with LPF, the average packet loss rate (PLR) of the overall system can be cut down significantly without increasing the buffer storage, and with LSPF, the packets of the least important group will be discarded discriminately in the case of overflow to lower average PLRs of other groups. Moreover, SDP can cooperate with Ethernet's Backpressure Mechanism fairly well and be implemented easily on chip.
A method is presented for the short period and large chirped fiber grating fabrication. The relation of grating reflectivity with chirp parameter is discussed and various reflectivity gratings have been achieved under different UV exposal conditions. At last, a broad bandwidth filter with a free filter zone is obtained.
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