Digital coherent detection and wavelength division multiplexing are promising technologies for achieving throughputs from 100 Gb/s to Tb/s order in optical satellite communications. The adoption of these technologies leads to the possibility of using high performance, low cost commercial off the shelf (COTS) components for satellite communications. In this paper, as COTS optical devices and a DSP-ASIC suitable for enabling 100 Gb/s/wavelength capacity, a micro integrable tunable laser assembly, a lithium niobate modulator, a micro intradyne coherent receiver (Micro ICR) and a DSP-ASIC for 100 Gb/s fiber optical communications were successively exposed to a total fluence of more than 4.0 × 1010 p/cm2 of 70 MeV protons. This fluence is equivalent to the total non-ionizing dose (TNID) and total ionizing dose (TID) experienced during 10 years in low earth orbit. The components were powered, and the performance of a 100 Gb/s signal was measured during irradiation to assess the single event effect (SEE). All components showed no degradation as a result of TNID/TID effects. On the other hand, the Micro ICR and DSP-ASIC showed SEEs which required power cycling of the components to recover their functionality. The SEE affecting the DSP-ASIC also increased the post forward error correction bit error ratio (BER), but the BER nevertheless remained sufficiently low in practice. These radiation test results show that these COTS components can be good candidates for use in satellite communications.
For high capacity free space optical (FSO) communication systems, expected be used to support extended coverage for the sixth generation mobile service, the digital coherent technology and wavelength division multiplexing used in optical fiber communications are promising technologies. These technologies can generate optical signals supporting Tb/s level capacity. However, to achieve the link budget required for Tb/s optical links, transmit power in the order of 100 W is required, and achieving 100 W power output with an optical fiber amplifier is challenging. In this work we propose parallel optical amplification of channel groups split out from the WDM signal, instead of amplification of the undivided WDM signal, and the transmission of the amplified signals as separate beams passed through multi-aperture optics. This configuration can reduce the required output power from the individual optical fiber amplifiers. We designed the FSO terminals for the proposed configuration with 3 transmitter apertures, such that the apertures fell within the directivity of the FSO receiver terminal. We evaluated the configuration in an outdoor experiment with a 500 m FSO link and wavelength division multiplexed real-time 100 Gb/s digital coherent QPSK signals. The experimental results show that the proposed configuration can increase the total capacity by 3 times, from 200 Gb/s to 600 Gb/s, without needing to increase the output power from the individual optical fiber amplifiers.
KEYWORDS: Digital signal processing, Signal to noise ratio, Receivers, Clocks, Forward error correction, Field programmable gate arrays, Optical amplifiers, Signal detection
A combination of the coherent detection and digital signal processing (DSP) deployed in spectrally-efficient optical fiber communications is being applied to free space optical (FSO) communications. The DSP enables adaptive frequency offset compensation between the transmitter and receiver laser diodes (LDs), and also the adaptive equalization of the non-ideal frequency response of the optical and electrical devices, by continuously updating values for the phase rotation angles and the coefficients of equalization. Due to atmospheric turbulence, the SNR can suddenly be reduced, so that the adaptation will diverge from its optimum. Then, even if the SNR recovers, it will take much longer than usual for the adaptation to re-converge because it will be starting from a diverged value. In this paper, we propose to control the calculations for updating the adaptation with a state machine based on a SNR estimated from the extracted clock amplitude. The updated values are periodically written into FIFO registers when the SNR is higher than the receiver threshold, and when the SNR degrades, we fix the values using the output of the FIFO registers. This prevents divergence of the adaptation and enables reuse of the values before divergence, taking into account the fact that estimating the SNR takes a finite time. We designed the proposed DSPs, and confirmed that these designs can be implemented in field programmable gate arrays (FPGA). In an offline experiment we evaluated this model of the proposed DSP design using a 2.5 Gbaud quadrature phase shift keying (QPSK) signal. The experimental results showed that the proportion of error free time is increased from 91% to 98% by the proposed technique.
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