Mr. Syed Ali Hasnain Profile

Syed Ali Hasnain

at Texas A&M Univ

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Proceedings Article | 10 October 2020 Presentation + Paper

Towards reconfigurable optoelectronic hardware accelerator for reservoir computing

Syed Ali Hasnain, Rabi Mahapatra

Proceedings Volume 11547, 115470W (2020) https://doi.org/10.1117/12.2575401

KEYWORDS: Optoelectronics, Switches, Neural networks, Silicon, Computer architecture, Network architectures, Performance modeling, Modulators, Resonators, Analog electronics

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Reservoir Computing (RC) is a subset of Recurrent Neural Networks (RNN) and has emerged as a powerful method for large scale classification and prediction of temporal problems with a reduced training time. Silicon-Photonics architectures have enabled high speed hardware implementations of Reservoir Computing (RC). With a Delayed Feedback Reservoir (DFR) model, only one non-linear node can be used to perform RC. In literature, multi-layer photonic RC architectures have been proposed by stacking multiple reservoirs together. Such architectures have demonstrated improved performance over single reservoir networks. However, as we show in the paper, for each task, the performance improvements saturate with a different number of layers. Hence, a hardware accelerator with fixed number of reservoir layers is not optimal for all tasks. Moreover, the gain in performance also comes at the cost of increased power consumption. Therefore, in this paper we propose a new reconfigurable optoelectronic architecture for multi-layer RC. Our proposed architecture, is based on DFR model implemented by the use of Mach Zehnder Modulator (MZM) and on chip low loss delay lines for improved performance. It integrates photonic switches based on Micro Ring Resonators (MRR) to enable reconfigurability. The architecture enables layer selection and layer gating to select the number of layers required for a task. Selection of number of layers can optimize the architecture for a specific application, resulting in huge power savings, while maintaining the overall accuracy. Our experiments with NARMA task and analog speech recognition task show that by optimally configuring an up-to 4-layer architecture, power savings up to 40% can be achieved compared to state-of-the-art architectures while gaining up to 80% more accuracy. Our scalable architecture has an on-chip area overhead of 0.0184mm2 for a single delay line and MRR switch.

Proceedings Article | 10 October 2020 Poster + Presentation + Paper

Multilayer photonic reservoir computing architecture using time division multiplexing for parallel computation

Syed Ali Hasnain, Dharanidhar Dang, Rabi Mahapatra

Proceedings Volume 11547, 115471S (2020) https://doi.org/10.1117/12.2575402

KEYWORDS: Optical computing, Time division multiplexing, Computer architecture, Parallel processing, Optoelectronics, Analog electronics, Speech recognition, Neurons, Network architectures

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In the era of big data, large scale classification and prediction problems pose new challenges that the traditional VonNeumann architecture struggles to address. This calls for implementation of new computational paradigms. Photonic reservoir computing is a promising paradigm for large-scale classification and prediction problems. Reservoir Computing (RC) has three layers: the input layer, reservoir layer and output layer. The reservoir layer is a random interconnected network of neurons that is independent of the task being performed using RC. This enables a particular reservoir to be used for multiple tasks, as only the output layer needs to be trained. The independent nature of reservoir layer provides an opportunity for parallel processing of multiple tasks at the same time. Unfortunately, the optoelectronic architectures for RC in literature do not exploit this capability. Therefore, in this paper, we propose a multi-layer opto-electronic hardware architecture for parallel RC. Our architecture employs time division multiplexing to perform jobs in parallel. The implementation of the reservoir is based on Delayed Feedback Reservoir (DFR) model. In our experiments, we study the performance of different configurations of the proposed architecture for NARMA task and analog speech recognition task. We show that our architecture can outperform some of the leading single layer architectures by up to 90% for NARMA task while performing analog speech recognition in parallel and closely matches the performance of leading multi-layer photonic RC architectures with an increased error of 8% due to parallel processing. The proposed high-speed architecture has a power consumption of ~50W for a 4-layer network.

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