Proceedings Article | 15 April 2008
KEYWORDS: Clocks, Computer programming, Receivers, Standards development, Transmitters, Switches, Eye, Interfaces, Embedded systems, Connectors
High rate interconnections are important subsystems in modern data processing and control systems of many
classes. They are especially important in prospective embedded and on-board systems that used to be multicomponent
systems with parallel or distributed architecture, [1].
Modular architecture systems of previous generations were based on parallel busses that were widely used and
standardised: VME, PCI, CompactPCI, etc. Busses evolution went in improvement of bus protocol efficiency (burst
transactions, split transactions, etc.) and increasing operation frequencies. However, due to multi-drop bus nature and
multi-wire skew problems the parallel bussing speedup became more and more limited. For embedded and on-board
systems additional reason for this trend was in weight, size and power constraints of an interconnection and its
components.
Parallel interfaces have become technologically more challenging as their respective clock frequencies have
increased to keep pace with the bandwidth requirements of their attached storage devices. Since each interface uses a
data clock to gate and validate the parallel data (which is normally 8 bits or 16 bits wide), the clock frequency need only
be equivalent to the byte rate or word rate being transmitted. In other words, for a given transmission frequency, the
wider the data bus, the slower the clock.
As the clock frequency increases, more high frequency energy is available in each of the data lines, and a portion
of this energy is dissipated in radiation. Each data line not only transmits this energy but also receives some from its
neighbours. This form of mutual interference is commonly called "cross-talk," and the signal distortion it produces can
become another major contributor to loss of data integrity unless compensated by appropriate cable designs.
Other transmission problems such as frequency-dependent attenuation and signal reflections, while also
applicable to serial interfaces, are more troublesome in parallel interfaces due to the number of additional cable
conductors involved. In order to compensate for these drawbacks, higher quality cables, shorter cable runs and fewer
devices on the bus have been the norm. Finally, the physical bulk of the parallel cables makes them more difficult to
route inside an enclosure, hinders cooling airflow and is incompatible with the trend toward smaller form-factor
devices. Parallel busses worked in systems during the past 20 years, but the accumulated problems dictate the need for
change and the technology is available to spur the transition.
The general trend in high-rate interconnections turned from parallel bussing to scalable interconnections with a
network architecture and high-rate point-to-point links. Analysis showed that data links with serial information transfer
could achieve higher throughput and efficiency and it was confirmed in various research and practical design. Serial
interfaces offer an improvement over older parallel interfaces: better performance, better scalability, and also better
reliability as the parallel interfaces are at their limits of speed with reliable data transfers and others.
The trend was implemented in major standards' families evolution: e.g. from PCI/PCI-X parallel bussing to PCIExpress
interconnection architecture with serial lines, from CompactPCI parallel bus to ATCA (Advanced
Telecommunications Architecture) specification with serial links and network topologies of an interconnection, etc.
In the article we consider a general set of characteristics and features of serial interconnections, give a brief
overview of serial interconnections specifications. In more details we present the SpaceWire interconnection
technology. Have been developed for space on-board systems applications the SpaceWire has important features and
characteristics that make it a prospective interconnection for wide range of embedded systems.
