The grouping method assisted EPE-aware control method is being explored in a multi-feature dual layer Logic use case. EPE metric is estimated using angle resolved optical Scatterometry based overlay and electron beam-based metrology (large field of view SEM) for the reconstruction of edge-to-edge distance between the Metal and Via pattern. In the setup phase, EPE sensitivities to dose and focus have been derived using data from a FEM wafer. EPE-aware optimization, using scanner dose and overlay control sub-recipes, outperforms traditional optimization in simulations showing reduced EPE max per die. This improvement suggests a potential increase in device yield through the adoption of EPE-aware control strategies. To verify this performance improvement on wafers, an experiment is needed with minimal wafer to wafer and lot to lot variations which can be achieved by reducing time between lots and increasing the number of wafers measured.
For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.1 In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.
In this paper we have evaluated alignment and overlay for a Ruthenium Direct Metal Etch process. Depending on the integration strategy, line resistance and lithography requirements, a process with no remaining topography may be preferred from a lithography point of view, but due to the Ruthenium light absorption alignment and overlay through a thick Ruthenium layer will be challenging. In this paper we have studied the maximum thickness of Ruthenium for which the alignment sensor can still detect the alignment marks below and quantify the quality of diffraction-based overlay on an ASML YieldStar overlay metrology tool.
The key challenge to enable a good defectivity control for extreme ultraviolet (EUV) single expose at 32nm pitch is to understand what are the main drivers for defect generation.
CD is one of the main contributors, and has many sources of variability (reticle, imaging, die layout, scanner).
The paper will first discuss the quantification of defectivity sensitivity to CD, and identification of the main sources of CD variations (EUV flare, black border, etch, APC, mask bias etc...). All those effects do not have the same consequences on the defect level (only nanobridges will be considered as they are the main defect type).
At this pitch, CD margin is becoming critical, an any small variation can lead to pattern collapse/bridge regime.
In a second part, we will discuss the different options for a better CD control and evaluate their impact on the overall defectivity level (reticle, process and tool will be considered).
An Intrafield CD uniformity improvement of 40% can lead to a defect density reduction by about 30%.
Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice.
In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures.
As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.
While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches.
In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.
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