The technology evolution of 3D-NAND storage devices requires an extensive research and development (R and D) phase with frequent process changes during the film deposition, lithography and etching steps. These process changes might have an impact on the accuracy of overlay measurements, thereby influencing the on-product overlay performance. Besides, by increases of 3D-NAND storage density, the available space for overlay metrology error is significantly reduced. The combination of frequent process changes in R and D phase and tighter overlay metrology budget, increases the necessity of an accurate, yet robust overlay metrology solution that can be adopted for 3D-NAND development phase. In addition to that, such a metrology solution needs to have the ability of being smoothly transferred to the ramp and eventually to the high volume manufacturing (HVM) stage, where the metrology throughput is playing a significant role in terms of cost of ownership reduction. In this paper, we report the YieldStar multi-wavelength diffraction-based overlay (μDBO) metrology as a solution to address the above challenges. Unlike the conventional optical overlay metrology methods which use single light wavelength, this diffraction based technique uses multiple wavelengths to measure every single overlay metrology targets, which proves to be robust against process variation induced metrology errors. In order to demonstrate the advantages of this new metrology solution, the accuracy, robustness, and throughput performance of the multiwavelength μDBO metrology technique are evaluated in the YMTC 3D-NAND manufacturing process. In addition, a well-defined application strategy is developed for reducing the number of measurement wavelengths by the maturity level of process which results in a robustness gain without impacting the HVM throughput requirements.
Multilayer stack height in 3DNAND has reached the limit of the aspect ratio that etch technologies can cost-effectively achieve. The solution to achieve further bit density scaling is to build the stack in two tiers, each etched separately. While lowering the requirements on etch aspect ratio, stacking two tiers introduces a critical overlay at the interface between the stacks. Due to the height of each stack, stress- or etch-induced tilt in the channel holes is translated into overlay. Characterizing and controlling the resulting complex overlay fingerprints requires dense and frequent overlay metrology. The familiar electron beam metrology after etch-back (DECAP) is destructive and therefore too slow and expensive for frequent measurements. This paper will introduce a fast, accurate & robust data-driven method for In Device Overlay Metrology (IDM) on etched 3DNAND devices by making use of specially designed recipe setup targets. Also, potential applications for process control improvement will be demonstrated.
In this work a novel machine learning algorithm is used to calculate the after etch overlay of the memory holes in a 3DNAND device based on OCD metrology by YieldStar S1375. It is shown that the method can distinguish the overlay signals from the process induced signals in the acquired pupil image and therefore, enables for an overlay metrology approach which is highly robust to process variations. This metrology data is used to characterize and correct the process induced intra-die stress and the DUV scanner application fingerprint.
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