Advancing technology nodes in CMOS Image Sensors (CIS) continues to drive a shrinking process to acquire higher resolution and low power consumption as well as more cost-effective production. With the sensor pixel size scaling down, a thicker photoresist (with aspect ratios greater than 10:1) is introduced to block high-energy implants with extremely localized implant profiles. Then double exposures/double focus (DE/DF) is applied to make sure the resist profile and process window is comparable or better. However, this process is a big challenge at high volume manufacturing (HVM) phase because of throughput loss. To recover it due to DE/DF, we invented SE MFI which uses two wavelengths (“colors”) generated by the KrF excimer laser to solve the problem. Due to the chromatic aberrations in the lens, the focal plane shift of different wavelength produces nearly the same result as DE/DF. However, the use of two-wavelengths brings some challenges. The first is the loss of image contrast and the second is the impact of chromatic aberrations across the slit which results in image shift and image asymmetry. In this work, we demonstrated that the use of ASML’s Tachyon KrF MFI source mask optimization (SMO) that can match the MFI SE process to DE/DF process of record (POR). We first used Tachyon Focus-Exposure Modeling plus (FEM+) to calibrate a DE resist model by using DE POR wafer data. Then we converted the DE model to a SE MFI model. At the end, we use the Tachyon MFI-SMO to optimize the SE MFI to match the DE/DF and MFI sidewall profiles through process window conditions at the center slit. We achieved making the MFI and DE/DF sidewall difference significantly smaller than other noises which can be measured on wafer at the center slit. We evaluated the chromatic aberration impact on through slit sidewall profiles also meet the specification. The through slit matching between MFI and DE/DF was further improved by through-slit mask optimization. This is done by inserting asymmetry sub resolution assist features (SRAFs). Tachyon Optical Proximity Correction plus (OPC+) can support full chip mask corrections for full-chip HVM. The above MFI technology including Tachyon optimization capability will be verified by wafer exposure via comparison between MFI and DE wafer results.
The technology evolution of 3D-NAND storage devices requires an extensive research and development (R and D) phase with frequent process changes during the film deposition, lithography and etching steps. These process changes might have an impact on the accuracy of overlay measurements, thereby influencing the on-product overlay performance. Besides, by increases of 3D-NAND storage density, the available space for overlay metrology error is significantly reduced. The combination of frequent process changes in R and D phase and tighter overlay metrology budget, increases the necessity of an accurate, yet robust overlay metrology solution that can be adopted for 3D-NAND development phase. In addition to that, such a metrology solution needs to have the ability of being smoothly transferred to the ramp and eventually to the high volume manufacturing (HVM) stage, where the metrology throughput is playing a significant role in terms of cost of ownership reduction. In this paper, we report the YieldStar multi-wavelength diffraction-based overlay (μDBO) metrology as a solution to address the above challenges. Unlike the conventional optical overlay metrology methods which use single light wavelength, this diffraction based technique uses multiple wavelengths to measure every single overlay metrology targets, which proves to be robust against process variation induced metrology errors. In order to demonstrate the advantages of this new metrology solution, the accuracy, robustness, and throughput performance of the multiwavelength μDBO metrology technique are evaluated in the YMTC 3D-NAND manufacturing process. In addition, a well-defined application strategy is developed for reducing the number of measurement wavelengths by the maturity level of process which results in a robustness gain without impacting the HVM throughput requirements.
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