Ms. Xichen Sheng Profile

Xichen Sheng

at ASML Shanghai

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Author

Publications (3)

Proceedings Article | 26 May 2022 Presentation + Paper

A novel solution on KrF pixel layer with thick photo resist (PR) by single exposure multi-focal imaging (SE MFI) technique

Zhenhai Yao, Lequn Jin, Yuhua Li, Maoqun Jiang, Fabin Huang, Min Fang, Xichen Sheng, Rongkuo Zhao, Michael Crouse, Chris Kaplan, Dongqing Zhang, Dongxiang Shi, Zhonghua Xu, Chaoqun Guo, Pieter Scheijgrond, Xiaoyang Jason Li, Stephen Hsu, Will Conley, Zhen Tang

Proceedings Volume 12051, 1205109 (2022) https://doi.org/10.1117/12.2616830

KEYWORDS: Semiconducting wafers, Chromatic aberrations, Data modeling, Calibration, Source mask optimization, Photomasks, SRAF, Copper indium disulfide, Optical lithography, Image processing

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Advancing technology nodes in CMOS Image Sensors (CIS) continues to drive a shrinking process to acquire higher resolution and low power consumption as well as more cost-effective production. With the sensor pixel size scaling down, a thicker photoresist (with aspect ratios greater than 10:1) is introduced to block high-energy implants with extremely localized implant profiles. Then double exposures/double focus (DE/DF) is applied to make sure the resist profile and process window is comparable or better. However, this process is a big challenge at high volume manufacturing (HVM) phase because of throughput loss. To recover it due to DE/DF, we invented SE MFI which uses two wavelengths (“colors”) generated by the KrF excimer laser to solve the problem. Due to the chromatic aberrations in the lens, the focal plane shift of different wavelength produces nearly the same result as DE/DF. However, the use of two-wavelengths brings some challenges. The first is the loss of image contrast and the second is the impact of chromatic aberrations across the slit which results in image shift and image asymmetry. In this work, we demonstrated that the use of ASML’s Tachyon KrF MFI source mask optimization (SMO) that can match the MFI SE process to DE/DF process of record (POR). We first used Tachyon Focus-Exposure Modeling plus (FEM+) to calibrate a DE resist model by using DE POR wafer data. Then we converted the DE model to a SE MFI model. At the end, we use the Tachyon MFI-SMO to optimize the SE MFI to match the DE/DF and MFI sidewall profiles through process window conditions at the center slit. We achieved making the MFI and DE/DF sidewall difference significantly smaller than other noises which can be measured on wafer at the center slit. We evaluated the chromatic aberration impact on through slit sidewall profiles also meet the specification. The through slit matching between MFI and DE/DF was further improved by through-slit mask optimization. This is done by inserting asymmetry sub resolution assist features (SRAFs). Tachyon Optical Proximity Correction plus (OPC+) can support full chip mask corrections for full-chip HVM. The above MFI technology including Tachyon optimization capability will be verified by wafer exposure via comparison between MFI and DE wafer results.

Proceedings Article | 23 March 2020 Presentation + Paper

Accurate etch modeling with massive metrology and deep-learning technology

Yifei Lu, Yuhang Zhao, Ming Li, Wei Yuan, Xiang Peng, Hongmei Hu, Shuxin Yao, Zhunhua Liu, Yu Tian, Ying Gao, Bingyang Pan, Weijun Wang, Chunyan Yi, Jinze Wang, Qian Xie, Xichen Sheng, Ying-chen Wu, Guanyong Yan, Yanjun Xiao, Liang Liu, Liang Ji, Qian Zhao, Yongfa Fan, Yiqiong Zhao, Mu Feng, Yueliang Yao, Terrance Yang, Jun Lang

Proceedings Volume 11327, 113270B (2020) https://doi.org/10.1117/12.2552001

KEYWORDS: Etching, Metrology, Calibration, Scanning electron microscopy, Data modeling, Optical proximity correction, Critical dimension metrology, Performance modeling, Image processing, Semiconducting wafers

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The semiconductor design node shrinking requires tighter edge placement errors (EPE) budget. OPC error, as one major contributor of EPE budget, need to be reduced with better OPC model accuracy. In addition, the CD (Critical Dimension) shrinkage in advanced node heavily relies on the etch process. Therefore AEI (After Etch Inspection) metrology and modeling are important to provide accurate pattern correction and optimization. For nodes under 14nm, the etch bias (i.e. the bias between ADI (After Development Inspection) CD and AEI CD) could be -10 nm ~ -50 nm, with a strong loading and aspect-ratio dependency. Etch behavior in advanced node is very complicated and brings challenges to conventional rule based OPC correction. Therefore, accurate etch modeling becomes more and more important to make precise prediction of final complex shapes on wafer for OPC correction. In order to ensure the accuracy of etch modeling, high quality metrology is necessary to reduce random error and systematic measurement error. Moreover, CD gauges alone are not sufficient to capture all the effects of the etch process on different patterns. Edge placement (EP) gauges that accurately describe the contour shapes at various key positions are needed. In this work we used the AEI SEM images obtained from traditional CD-SEM flow, processed with ASML’s MXP (Metrology for eXtreme Performance) tool, and used the extracted CD gauges and massive EP gauges to train a deeplearning Newron Etch model. In the approach, MXP reduced the AEI metrology random errors and shape fitting measurement error and provides better pattern coverage with massive reliable CD and EP gauges, Newron Etch captures complex and unknown physical and chemical effects learned from wafer data. Results shows that MXP successfully extracted stable contour from AEI SEM for various pattern types. Three etch models are calibrated and compared: CD based EEB model (Effective Etch Bias), CD+EP based EEB model, and CD+EP based Newron etch model. CD based EEB model captures the major trend of the etch process. Including EP gauges helps EEB model with about 10% RMS reduction on prediction. Integration of MXP (CD+EP) and Newron Etch model gains about 45% prediction RMS reduction compared to baseline model. The good prediction of Newron Etch is also verified from wafer SEM overlay on complex-shape patterns. This result validates the effectiveness of ASML’s solution of deep learning etch model integration with MXP AEI’s massive wafer data extraction from etch process, and will help to provide accurate and reliable etch modeling for advanced node etch OPC correction in semiconductor manufacturing.

Proceedings Article | 17 May 2019 Paper

Metrology and deep learning integrated solution to drive OPC model accuracy improvement

Wei Yuan, Yifei Lu, Yuhang Zhao, Shoumian Chen, Ming Li, Hongmei Hu, Shuxin Yao, Zhunhua Liu, Qiaoqiao Li, Yu Tian, Zhiquan Zhou, Lirong Gu, Jinze Wang, Xichen Sheng, Guanyong Yan, Yazhong Zheng, Yueliang Yao, Yanjun Xiao, Liang Liu, Qian Zhao, Mu Feng, Jun Chen, Jun Lang

Proceedings Volume 10961, 109610N (2019) https://doi.org/10.1117/12.2516236

KEYWORDS: Metrology, Calibration, Data modeling, Scanning electron microscopy, Optical proximity correction, Performance modeling, Critical dimension metrology, Semiconducting wafers, Image processing, Photomasks

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