Mr. Yanjun Xiao Profile

Yanjun Xiao

at ASML

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Publications (4)

Proceedings Article | 23 March 2020 Presentation + Paper

Accurate etch modeling with massive metrology and deep-learning technology

Yifei Lu, Yuhang Zhao, Ming Li, Wei Yuan, Xiang Peng, Hongmei Hu, Shuxin Yao, Zhunhua Liu, Yu Tian, Ying Gao, Bingyang Pan, Weijun Wang, Chunyan Yi, Jinze Wang, Qian Xie, Xichen Sheng, Ying-chen Wu, Guanyong Yan, Yanjun Xiao, Liang Liu, Liang Ji, Qian Zhao, Yongfa Fan, Yiqiong Zhao, Mu Feng, Yueliang Yao, Terrance Yang, Jun Lang

Proceedings Volume 11327, 113270B (2020) https://doi.org/10.1117/12.2552001

KEYWORDS: Etching, Metrology, Calibration, Scanning electron microscopy, Data modeling, Optical proximity correction, Critical dimension metrology, Performance modeling, Image processing, Semiconducting wafers

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The semiconductor design node shrinking requires tighter edge placement errors (EPE) budget. OPC error, as one major contributor of EPE budget, need to be reduced with better OPC model accuracy. In addition, the CD (Critical Dimension) shrinkage in advanced node heavily relies on the etch process. Therefore AEI (After Etch Inspection) metrology and modeling are important to provide accurate pattern correction and optimization. For nodes under 14nm, the etch bias (i.e. the bias between ADI (After Development Inspection) CD and AEI CD) could be -10 nm ~ -50 nm, with a strong loading and aspect-ratio dependency. Etch behavior in advanced node is very complicated and brings challenges to conventional rule based OPC correction. Therefore, accurate etch modeling becomes more and more important to make precise prediction of final complex shapes on wafer for OPC correction. In order to ensure the accuracy of etch modeling, high quality metrology is necessary to reduce random error and systematic measurement error. Moreover, CD gauges alone are not sufficient to capture all the effects of the etch process on different patterns. Edge placement (EP) gauges that accurately describe the contour shapes at various key positions are needed. In this work we used the AEI SEM images obtained from traditional CD-SEM flow, processed with ASML’s MXP (Metrology for eXtreme Performance) tool, and used the extracted CD gauges and massive EP gauges to train a deeplearning Newron Etch model. In the approach, MXP reduced the AEI metrology random errors and shape fitting measurement error and provides better pattern coverage with massive reliable CD and EP gauges, Newron Etch captures complex and unknown physical and chemical effects learned from wafer data. Results shows that MXP successfully extracted stable contour from AEI SEM for various pattern types. Three etch models are calibrated and compared: CD based EEB model (Effective Etch Bias), CD+EP based EEB model, and CD+EP based Newron etch model. CD based EEB model captures the major trend of the etch process. Including EP gauges helps EEB model with about 10% RMS reduction on prediction. Integration of MXP (CD+EP) and Newron Etch model gains about 45% prediction RMS reduction compared to baseline model. The good prediction of Newron Etch is also verified from wafer SEM overlay on complex-shape patterns. This result validates the effectiveness of ASML’s solution of deep learning etch model integration with MXP AEI’s massive wafer data extraction from etch process, and will help to provide accurate and reliable etch modeling for advanced node etch OPC correction in semiconductor manufacturing.

Proceedings Article | 17 May 2019 Paper

Metrology and deep learning integrated solution to drive OPC model accuracy improvement

Wei Yuan, Yifei Lu, Yuhang Zhao, Shoumian Chen, Ming Li, Hongmei Hu, Shuxin Yao, Zhunhua Liu, Qiaoqiao Li, Yu Tian, Zhiquan Zhou, Lirong Gu, Jinze Wang, Xichen Sheng, Guanyong Yan, Yazhong Zheng, Yueliang Yao, Yanjun Xiao, Liang Liu, Qian Zhao, Mu Feng, Jun Chen, Jun Lang

Proceedings Volume 10961, 109610N (2019) https://doi.org/10.1117/12.2516236

KEYWORDS: Metrology, Calibration, Data modeling, Scanning electron microscopy, Optical proximity correction, Performance modeling, Critical dimension metrology, Semiconducting wafers, Image processing, Photomasks

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Proceedings Article | 20 March 2019 Paper

Optimal feature vector design for computational lithography

Xuelong Shi, YuHang Zhao, Shoumian Cheng, Ming Li, Wei Yuan, Leon Yao, Wenhao Zhao, Yanjun Xiao, Xiaohui Kang, Angmar Li

Proceedings Volume 10961, 109610O (2019) https://doi.org/10.1117/12.2515446

KEYWORDS: Computational lithography, Machine learning, Neural networks, Data modeling, Optical proximity correction, Lithography, Feature extraction, Convolution, Physics, Process modeling

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Proceedings Article | 30 October 2007 Paper

Production-worthy full chip image-based verification

Zongchang Yu, Youping Zhang, Yanjun Xiao, Wanyu Li

Proceedings Volume 6730, 67300T (2007) https://doi.org/10.1117/12.747022

KEYWORDS: Artificial intelligence, Inspection, Optical proximity correction, Evolutionary algorithms, Printing, Metals, Tolerancing, Feature extraction, Computer simulations, Sensors

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At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional model-based verification at only the nominal condition. Full-chip, full process-window verification has started to integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based approach for post-OPC verification in detail. For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging. Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed situation. At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers. We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show the performance of the full-chip image-based verification.

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