The CMOS IC industry thrives on the down-scaling drive for ever smaller transistors, leading to faster, smaller and more complex digital systems. These ICs are interconnected by electrical tracks running on Printed Circuit Boards. Due to different frequency-dependent sources of signal degradation, the performance of these electrical interconnects lags behind the IC performance. As the electrical interconnect bottleneck increasingly impacts overall system performance, the interest in optical interconnects at the inter-chip level is growing. An important question to answer is how and where such optical interconnects should be implemented. Therefore, we first discuss the weaknesses of electrical interconnects and the potential benefits of optical interconnects. From this we then consider the implications on the introduction of optical interconnects and we argue why integration is of key importance for the successful introduction of optical interconnects at this level. Finally we describe how we have implemented optical inter-chip interconnects in a demonstrator system and go into more detail on the different levels of integration in this demonstrator system.
Ronny Bockstaele, Michiel De Wilde, Wim Meeus, Olivier Rits, Hannes Lambrecht, Jan Van Campenhout, Johan De Baets, Peter Van Daele, Eric van den Berg, Michaela Klemenc, Sven Eitel, Richard Annen, Jan Van Koetsem, Gilles Widawski, Jacques Goudeau, Baudouin Bareel, Patrick Le Moine, Reto Fries, Peter Straub, Francois Marion, Julien Routin, Roel Baets
This paper describes a complete technology family for parallel optical interconnect systems. Key features are the two-dimensional on-chip optical access and the development of a complete optical pathway. This covers both chip-to-chip links on a single boards, chip-to-chip links over an optical backpanel, and even system-to-system interconnects. Therefore it is a scalable technology. The design of all parts of the link, and the integration of parallel optical interconnect systems in the design flow of electronic systems is presented in this paper.
In order to satisfy the increasing demand for interchip interconnect bandwidth, a number of current research projects are concentrating on the use of waveguided optical interconnect arrays to span PCB-range distances. To accelerate system design and technology development, CAD tools for the design and the simulation of the interconnects are indispensable. We are developing a design methodology for optical inter-chip interconnects, to produce a tool for assisting system designers on deciding on product and parameter options for the different interconnect building blocks. A mandatory first step in this methodology development concerns the investigation of the combined impact of individual product and parameter variations on system-level interconnect system properties. Accurately predicting some interconnect properties requires analog simulation of the full electrical-optical-electrical links. Detailed models for the link building blocks involving geometrical calculations are much too slow for this purpose. Circuit-level simulation tools, with appropriate model descriptions, are much more suitable. In this paper, we describe our framework for the joint simulation of the entire optical interconnect with a mixed analog/digital system. We discuss in detail a number of issues that are involved with the implementation of circuit-level simulation models in the analog modelling language Verilog-AMS, and show a link simulation example.
Centimeter-range high-density optical interconnect between chips is coming into reach with current optical interconnect technology. Many theoretical studies have identified several good reasons why to use such types of interconnect as a replacement of various layers of the traditional electronic interconnect hierarchy. However, the true feasibility and usefulness of optical interconnects can only be established by actually building and evaluating them in a real system setting. This contribution reports on our experience in using short-range high-density optical inter-chip interconnects. It is based on the design and construction of a fully functional optoelectronic demonstrator system. We discuss the rationale for building the demonstrator in the first place, the implications of using many low-level optical interconnections in electronic systems, and the degree to which our expectations have been fulfilled by the demonstrator. The detailed description of the architecture, design and implementation of the demonstrator is not presented here, but can be found elsewhere in this issue.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.