Expertise in Systems Application, Engineering and Product Management of Semiconductor Optical Metrology Systems.
US Patent # 6,612,159 B1, Taiwan Patent NI-163761, Sole Author, “Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers.”
US Patent #10,445,889 b2, Sole Author, “Method of measuring offset in an integrated circuit and related technology” (Diamond Algorithm) to provide better repeatability and TIS on Box in Box overlay structures
US Patent # 6,612,159 B1, Taiwan Patent NI-163761, Sole Author, “Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers.”
US Patent #10,445,889 b2, Sole Author, “Method of measuring offset in an integrated circuit and related technology” (Diamond Algorithm) to provide better repeatability and TIS on Box in Box overlay structures
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