With the increasing complexity of semiconductor manufacturing processes, from early R&D through ramp and high-volume manufacturing (HVM), a myriad of data analysis solutions are required for fast and actionable decisions in a fab. In our previous work, we used the SEM metrology capabilities of aiSIGHT to perform shape analysis and defect detection of contact holes and pillars in tight-pitch DRAM structures such as storage node landing pad arrays (SNLP) to gain insights on process variability. This paper focuses on a different type of metrology application, extracting unbiased roughness from mask and wafer SEM images, such as unbiased line edge roughness (LER) and line width roughness (LWR), along with defect detection.
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