Ever since IBM pioneered microelectronics packaging, IBM Research has continued to innovate to ensure that packaging and heterogeneous integration technology is available to satisfy the needs for performance, complexity, and memory and logic density with regard to high performance computing systems. In this era of ever-expanding need for high-performance computing and ever-pervasive artificial intelligence, traditional scaling economics headwinds combined with the need for versatility and fast product development mandate a system-level approach to generate the efficiencies the industry has been able to provide in the past through more traditional scaling approaches. This system-level approach renders imperative the use of chiplet-based architectures and the use of heterogeneous integration and advanced packaging to achieve the disaggregation with best-performing and most efficient IP components to sustain a viable economic model while achieving performance targets. In this talk we will discuss several key process and integration considerations that drive the use of various horizontal and vertical interconnection technology elements that must be implemented to enable the successful realization of efficient and cost-effective high-performance systems in the AI era. Future progress on these technology fronts will depend on disruptive innovation in two critical areas: (a) wafer-level and die-level processes, such as lithographic patterning, wafer-wafer bonding and debonding, bond and assembly processes, etc. that can enable packaging of these heterogeneous structures without compromising performance and reliability, (b) commensurate improvements and enablement of adequate metrology and inspection solutions to address the challenges stemming from these new chiplet-interconnecting methods and the associated topographic implications.
Satellite spot defects are a class of defects widely observed in photoresist processing in 248 nm and 193 nm lithography. These defects become more and more significant as the feature sizes shrink and can potentially become “killer” defects, leading to bridging between lines and/or blocking vias. Traditional potential solutions (i.e., optimization of development rinse step) have yielded improvements in the past but did not eliminate the problem. The use of water-soluble topcoat layers was shown to eliminate these defects but it imposes limitations on throughput and cost and it is incompatible with 157 nm lithography and 193 nm immersion schemes. In this work, we report the use of aqueous surfactant solutions for the suppression of defects in 248 nm and 193 nm lithography, with emphasis on satellite spot defects. Suppression of total defects by up to ~99% and practically complete elimination of satellite spot defects were achieved by use of aqueous surfactant solutions for various resists. A handful of materials that can be incorporated into rinse solution for the successful elimination of blob defects in a variety of resists were identified. It was determined that the two most important factors that enable successful defect elimination are the surfactant concentration and the extent of surfactant adsorption to specific resist systems.
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