Dr. Tejas Jhaveri Profile

Dr. Tejas Jhaveri

Student Researcher at Carnegie Mellon Univ

SPIE Involvement:

Author

Publications (14)

Proceedings Article | 4 April 2011 Paper

Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes

Vyacheslav Rovner, Tejas Jhaveri, Daniel Morris, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7974, 79740I (2011) https://doi.org/10.1117/12.879514

KEYWORDS: Logic, Manufacturing, Silicon, Source mask optimization, Optical lithography, Multiplexers, Neodymium, Connectors, Chemical mechanical planarization, Radon

Read Abstract +

Proceedings Article | 4 April 2011 Paper

Using templates and connectors for layout pattern minimization in 20nm and below technology nodes

Tejas Jhaveri, Andrzej Strojwas

Proceedings Volume 7974, 797405 (2011) https://doi.org/10.1117/12.879234

KEYWORDS: Connectors, Source mask optimization, Logic, Lithography, Neodymium, Aerospace engineering, Computational lithography, Manufacturing, Electroluminescence, Design for manufacturing

Read Abstract +

Proceedings Article | 8 June 2010 Paper

Design compliant source mask optimization (SMO)

Robert Socha, Tejas Jhaveri, Mircea Dusa, Xiaofeng Liu, Luoqi Chen, Stephen Hsu, Zhipan Li, Andrzej Strojwas

Proceedings Volume 7748, 77480T (2010) https://doi.org/10.1117/12.865781

KEYWORDS: Source mask optimization, Photomasks, Photovoltaics, Logic, Feedback loops, Lithography, Metals, Electroluminescence, Diffractive optical elements, Manufacturing

Read Abstract +

Proceedings Article | 3 April 2010 Paper

Demonstrating the benefits of template-based design-technology co-optimization

Lars Liebmann, Jason Hibbeler, Nathaniel Hieter, Larry Pileggi, Tejas Jhaveri, Matthew Moe, Vyacheslav Rovner

Proceedings Volume 7641, 76410R (2010) https://doi.org/10.1117/12.848244

KEYWORDS: Logic, Manufacturing, Yield improvement, Logic devices, Legal, Semiconductors, Design for manufacturability, Lithography, Model-based design, Process modeling

Read Abstract +

Proceedings Article | 3 April 2010 Open Access

Application of the cost-per-good-die metric for process design co-optimization

Tejas Jhaveri, Umut Arslan, Vyacheslav Rovner, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7641, 764104 (2010) https://doi.org/10.1117/12.846556

KEYWORDS: Lithography, Process engineering, Manufacturing, Design for manufacturability, Current controlled current source, Semiconductors, Semiconducting wafers

Read Abstract +

DOWNLOAD PAPER

Proceedings Article | 3 April 2010 Paper

Layout pattern minimization for next-generation technologies

Tejas Jhaveri, Andrzej Strojwas

Proceedings Volume 7641, 764108 (2010) https://doi.org/10.1117/12.846367

KEYWORDS: Source mask optimization, Design for manufacturability, Current controlled current source, Computational lithography, Estimation theory

Read Abstract +

Proceedings Article | 23 September 2009 Paper

Economic assessment of lithography strategies for the 22nm technology node

Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi, Vyacheslav Rovner

Proceedings Volume 7488, 74882Y (2009) https://doi.org/10.1117/12.837240

KEYWORDS: Lithography, Semiconducting wafers, Source mask optimization, 193nm lithography, Optical lithography, Manufacturing, Dysprosium, Electron beam lithography, Double patterning technology, Process modeling

Read Abstract +

Proceedings Article | 16 March 2009 Paper

OPC simplification and mask cost reduction using regular design fabrics

Tejas Jhaveri, Ian Stobert, Lars Liebmann, Paul Karakatsanis, Vyacheslav Rovner, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7274, 727417 (2009) https://doi.org/10.1117/12.814406

KEYWORDS: Optical proximity correction, Photomasks, Model-based design, Metals, Lithography, Manufacturing, Optical lithography, Double patterning technology, Inspection, Yield improvement

Read Abstract +

Proceedings Article | 13 March 2009 Paper

Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond

Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop

Proceedings Volume 7275, 72750A (2009) https://doi.org/10.1117/12.814701

KEYWORDS: Logic, Metals, Lithography, Optical lithography, Design for manufacturing, Yield improvement, Model-based design, Diffusion, Transistors, Process modeling

Read Abstract +

Proceedings Article | 7 March 2008 Paper

Enabling technology scaling with "in production" lithography processes

Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi, Vyachelav Rovner

Proceedings Volume 6924, 69240K (2008) https://doi.org/10.1117/12.776484

KEYWORDS: Lithography, Metals, Front end of line, Optical lithography, Photomasks, Manufacturing, Optical design, Transistors, Standards development, Double patterning technology

Read Abstract +

SPIE Journal Paper | 1 July 2007

Maximization of layout printability/manufacturability by extreme layout regularity

Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej Strojwas, Dipti Motiani, Veerbhan Kheterpal, Kim Yaw Tong, Thiago Hersan, Davide Pandini

JM3, Vol. 6, Issue 03, 031011, (July 2007) https://doi.org/10.1117/12.10.1117/1.2781583

KEYWORDS: Logic, Metals, Manufacturing, Lithography, Standards development, Silicon, Integrated circuit design, Design for manufacturability, Optical proximity correction, Resolution enhancement technologies

Read Abstract +

Proceedings Article | 24 March 2006 Paper

Maximization of layout printability/manufacturability by extreme layout regularity

Tejas Jhaveri, Larry Pileggi, Vyacheslav Rovner, Andrzej Strojwas

Proceedings Volume 6156, 615609 (2006) https://doi.org/10.1117/12.659984

KEYWORDS: Logic, Metals, Manufacturing, Lithography, Silicon, Resolution enhancement technologies, Standards development, Design for manufacturability, Image quality, Optical proximity correction

Read Abstract +

Proceedings Article | 12 May 2005 Paper

Investigation of viable approaches to AAPSM intensity imbalance reduction for 65nm lithography

Tejas Jhaveri, Rand Cottle, Yuan Zhang, Christopher Progler

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.593219

KEYWORDS: Manufacturing, Photomasks, Electroluminescence, Etching, Critical dimension metrology, Lithography, Standards development, Phase shifts, Scanning electron microscopy, Optics manufacturing

Read Abstract +

Proceedings Article | 2 June 2003 Paper

Rotation-induced measurement error by a CD-SEM

Tejas Jhaveri, Rand Cottle

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485030

KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Data modeling, Metrology, Semiconductors, Calibration, Manufacturing, Optical alignment, Photomasks, Lithography

Read Abstract +

Showing 5 of 14 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years