In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layer-division realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.
In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high- NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.
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