Etching damage is evaluated by the forward current characteristics of p+/n+ junction s formed directly on the damaged silicon surface. The sample has a double layer structure (poly-silicon/silicon dioxide), and the poly-silicon layer is removed by dry etching with gas plasma. The degree of degradation of the forward current characteristics by reactive ion etching (RIE; cathode coupling mode) is greater than that by plasma etching (PE; anode coupling mode). In the RIE mode, heavier damage is accumulated at the surface by the bombardment of high energy ions through the thin oxide layer and causes the recombination current. This evaluation method is sensitive and useful, and it can detect the very small radiation damage.

Wafer charging in barrel etchers, reactive ion etching (RIE) etchers, magnetron RIE (MRIE) etchers and electron cyclotron resonance (ECR) etchers are characterized. The charging voltages were measured by using electrically programmable non-volatile memories. The charging profile for the barrel etchers and the RIE etcher depends critically on the electrode arrangements and wafer locations, while that in the MRIE etchers and the ECR etchers depends on the structure of the magnetic field. Even in the case of a non-divergent magnetic field ECR etcher, wafer charging is built-up when an RF bias is applied to the wafer stage. By analyzing these results, two charging mechanisms are distinguished. One is the plasma nonuniformity around the wafer, which depends on the RF electrode and the wafer location. The other is the anisotropy of the magnetized plasma, which depends on the structure of the magnetic field. Some of the charging profiles due to the former effect is reproduced by using an equivalent circuit model. It is found from the model that even in the uniform density plasma, wafer charging is induced by the RF current which causes a plasma potential variation across the wafer surface.

Production of quality devices with high yield requires low contamination process environments. In particular, trace levels of moisture and by-product generated particles will lead to defects and loss of device yield. It is well established that chip sizes are increasing, while the feature sizes of these devices are headed towards 0.35 micron and below by the early to mid 1990s. These small features are sensitive to the population of previously insignificantly-sized particles, which were always present but did not cause high yield loss. Smaller feature sizes are more sensitive to process contamination. Previous work has shown that particles generated during process are often the results of the chemistry in use 1 . In oxide etching halocarbons are commonly used. These gases are known to generate carbon based polymers, which are a recognized source of process generated particles. An in situ process has been developed to minimize thegeneration and accumulation of by-products. Particle data and process reproducibility data will be presented using this auto ash technique.

A LDD (lightly doped drain) etch process has been developed that reduces the damage to the silicon substrate caused by the oxide etch step and removes the damaged silicon in a subsequent etch step. The underlying silicon has the damage level restored to that of unetched silicon, as measured with thermal wave modulated reflectance. Contact resistivity of the devices etched with the optimum etch process is substantially reduced compared to a standard process.

Reactive ion etching (RIE) is developed by employing NF3 gas in order to avoid the fluorocarbon contamination on the Si surface exposed to the plasma. A high SiO2 etch rate is achieved with magnetically enhanced RIE because of efficient species generation. An anisotropic etching profile of SiO2 is obtained due to the low pressure and low temperature operation. The reaction layers on Si surfaces are investigated by x-ray photoelectron spectroscopy and cross-sectional transmission electron microscopy. It is found that the NF3 plasma etching is more effective to maintain a clean surface than the CHF3 plasma etching. In addition the photoresist which is used as a mask during via-hole etching is easily removed without any residues by O2 plasma ashing because the fluorocarbon contamination is avoided.

In order to find out the factors determining the resolution on the resist silylated process, we evaluated factors for each stage of pattern generation process. It is found that the silylated layer is formed as a result of the light energy distribution. Moreover, it can be explained that side etching brought about the degradation of vertical etching rate in fine slits (micro-loading effect). This micro-loading effect degrades the resolution slightly. Using a condition with minimized micro-loading effect, we obtained patterns with near vertical sidewall and with small linewidth difference between packed and isolated lines.

The paper deals with the simulation of the etching step of resists containing silicon, Hith special attention on DESIRE technology, for which purpose a general mathematical model is built which emphasizes the role of the gas-solid reaction at the interface plasma/polymer. Some preliminary simulation results are presented.

The diffusion enhanced silylated resist or DESIRER process is a well known surface imaging lithographic technique consisting of three steps: exposure, silylation, and dry develop. The success of this method for patterning submicron features depends critically on controlling silicon incorporation in the resist. In this report interferometric data obtained during the resist silylation step and subsequent dry develop etch have been used to correlate silylation parameters and exposure dose with the depth of silicon incorporation. Contrast and linewidth variation as a function of silylation depth have been derived. A kinetics model in conjunction with image intensity simulations has been used to understand the effects of process parameters on pattern quality. The potential of using the interferometric data for process monitoring is also discussed.

Photoresist dry etching processes by a down-stream type ECR plasma etcher were characterized. The etched photoresist profile and etch rates were obtained by scanning electron microscope (SEM) photographs and an optical thickness monitoring instrument, respectively. The mask used for PR etch tests has 1 um pitched line & space patterns. It was found that C12 addition to 02 plasma can passivate PR side walls. The etch profiles of PR vary critically with the main coil current changes. The etch rate has maximum of 4800 Å/min and the etch uniformity has a minimum value of 5.4 %. The dc bias voltage (Vdc) variations are closely related to the etch profiles. Vdc decreases when PR etching is completed and substrates are exposed to the plasma. The wafers with different thin film materials induce different Vdc for a same process condition. The plasma properties were measured by a Langmuir probe. The N2 addition to 02 plasma were also tested. However, the critical effect of the main coil current was not found for the N2 processes. A model was formulated to explain the difference between C12 processes and N2 processes with an equivalent circuit method.

This paper describes the effect of process condition on the resist profile in the DESIRE process[l,2] ,which is one of the surface imaging process, has some advantages compared with conventional photo lithography process. In our previous study on the resist profile, it was indicated that pattern formation was strongly depended on the silylated layer and the degree of sidewall protection during dry-development[3]. Then, we studied the effect of sidewall protection under various process factors such as soft-bake, silylation, and various resist materials. From the results of the study, it was found that the degree of sidewall protection could be controlled by the process conditions, attributed to silylated profile and the degree of silylation. Clear tendency that silylated profile leaving a trail gave a vertical sidewall profile was observed. Furthermore, it was found that silicon dioxide was observed on the sidewall surface of resist pattern by Micro Auger Electron Spectroscopy. The silicon dioxide seems to act as an inhibiting layer for lateral etching during Oxygen RLE. We will also report the mechanism consideration of sidewall protection during dry-development. Consequently, through the whole process optimization, 0.3?m L/S resist pattern resolution and 1.4?m wide focus range at 0.36?m L/S with a thickness 1.2?m are successfully obtained even in a single layer using i-line stepper with NA 0.50.

ULSI device manufacturing requires capital equipment manufacturers to deliver state of the art performance, particle-free process environments, and high uptime. With critical dimensions of 0.5 ? and below, essentially perfect etching results are required to meet device requirements. Gate structures, once simple poly-si types, are now multiple films of poly-si plus silicide. Contact hole etching to silicon requires damage free and polymer free surfaces following etch. Metallizations, once single aluminum alloy films, are now complex refractory metal/aluminum/refractory metal sandwiches. Multiple etch steps are required to successfully process these layers. Drytek has manufactured integrated process equipment for the past six years. To meet the demand for ULSI, Drytek has developed the ASIQ™, or Application Specific Integrated Quad. Our paper will discuss the benefits of the ASIQ™ system concept for complex etch applications, where the use of different plasma sources on the same integrated process platform is required for near perfect etching results of ULSI devices.

The business climate of the integrated circuit industry in the 1990's is very different from that of the 1970's. Today's industry demands that manufacturers produce newer more complex designs with shrinking design time windows and higher return on investment for fabrication facilities. This tighter business climate inposes stricter controls on the day to day operation of the fabrication process. Now, not only must new equipment make significant improvements in process capability but every effort must be made to insure that older (already depreciated) equipment is used to its fullest. To this end extensive work has been undertaken to establish "sensor based manufacturing" (SBM) schemes with the goal of improving wafer to wafer as well as within a wafer repeatability and extending equipment useful lifetime. This improvement in repeatability translates into reduced need for expensive, time consuming, in-line metrology. The end result is improved cycle time and reduced overall facility costs. Early work on this topic centered around the generation of a parametrical view of the plasma process module. By viewing the module as the convolution of a plasma based chemical factory and the hardware necessary to establish and sustain it, a scheme for improved control becomes clear. Present control schemes are based only on hardware or machine parameters, yet the wafer results are defined by the plasma parameters. Therefore, shifting the focus of module control from the traditional machine parameters to the less conventional plasma parameters would place the focus of control closer to the wafer and improve process performance. This paper deals with the application of SBM concepts to establish the real time monitoring of fundamental machine and plasma parameters known to have direct correlation to wafer results such as etch rate and uniformity. Proper usage of SBM generated information includes improved end point capabilities, real time SPC and "go-no-go" decision analysis.

Two approaches to etching of copper have been identified. The first approach involves generating various adducts of CuX where X = Cl or Br, LnCuX, where n = 1 or 2 and L is a Lewis base. Various compounds with general formula LnCuX have been identified where L = PMe3, PEt3, P(i-Pr)3, and PBU3. The second approach involves the reaction of Cu films with Cu(hfac)2 (where hfac = 1,1,1,5,5,5- hexafluoroacetylacetonate) and various L to form two equivalents of (hfac)CuL. Various (hfac)CuL species have been identified where L = alkyne (2-butyne, bis-trimethylsilyl acetylene, pentyne), olefin (1,5-cylooctadiene, vinyltrimethylsilane) and PR3 (PMe3, PEt3). Spontaneous etching experiments have been carried out using copper films in a hot-wall reactor. Etch rates up to 1 pm/min have been achieved at temperatures below 150°C. The high etch rates are the result of the high vapor pressures of the LnCuX and (hfac)CuL which are on the order of 0.1 -1 Torr at 60-100°C. The application of these and other chemical approaches to plasma and laser etching of copper is under investigation.

Reactive-ion-etching (RIE) induced surface modifications of SiO2 and phosphosilicate glass (PSG) were investigated using thermal desorption mass spectroscopy (TDS) and X-ray photoelectron spectroscopy (XPS), in order to study their reactivity variance in the highly polymerized fluorocarbon plasma. Ar+ induced reactions between the fluorocarbon adsorption layer and the underlying oxide substrates were also examined. At the C,F-film/substrate interface, the adsorption layer was found to be chemisorbed to the substrates. Both SiO2 and PSG were found to react in a very near surface region, chiefly with the adsorption layer, by reflecting the reactivity in SiOxFy reaction layer below the surface. The mechanisms of the reactivity variance were explained by the difference in density of active sites for unsaturated CFX chemisorption induced by ion bombardment, and the variance of Si-O bond breakability of the substrates. These effects are caused by the existence of P-O or P = 0 bonds in PSG. Fluorocarbon chemisorption layers were also observed to be thermally stimulated to react with the substrates in TDS apparatus with to activation energy of approximately 1.9eV. This observation indicates the possibility that chemical sputtering easily occurs in actual RIE through a thermally excited step, induced by ion bombardment.

The paper discusses a Chemically Assisted Ion Beam Etching (CAIBE) technique for etching of GaAs and GaSb based on reactive flux of iodine vapours derived from elemental iodine and Ar+ ion beam. The effect of iodine partial pressure in the range 0-14x10-5 torr has been studied on the etch rate of GaAs and GaSb at three different ion beam current densities. Initially, the etch rate increases with increase in iodine partial pressure; but at higher iodine flux the etch rate tends to attain saturation value. The Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) results show that uniform etching is obtained but at higher current density and high iodine flux etch pits start appearing. The high resolution electron microscopy (HREM) and electron diffraction studies show that no crystalline defects are introduced during Ar+/I2 CAIBE. The energy despersive analysis (EDS) of etched surface does not show presence of iodine. Thus the technique gives higher etch rate in comparison to only Ar+ ion beam without any art effect in terms of crystalline structure or surface contamination. The technique has been successfully used for anisotropic etching of 1.5 um test patterns using Dynachem OFPR-800 positive resit and for preparation of TEM specimen. The results on GaAs and GaSb are compared with those of Si, InP and InSb etching using Ar+/I2 CAIBE. A possible etch mechanism has been proposed to explain the etch behaviour.

We demonstrate a computer automated system for reactive sputter deposition of silicon and silicon nitride that features a laser reflectometer as an in-situ monitoring tool. A hollow anode was designed specifically for this purpose and enables in-situ reflectivity measurements at normal incidence to the wafer. We describe the use of this system for in-situ determination of the deposition rate and the material optical properties (refraedve index and loss). Finally we describe the fabrication of high precision Si/SiNx quarter-wave dielectric mirrors for opto-electronic applications by means of an in-situ feedback control algorithm.

Surface cleaning by pulsed UV-laser (wavelength = 193 nm) annealing in vacuo and laser-enhanced oxidation of GaSb single crystals in air are investigated by Auger and X-ray photoelectron spectroscopies. Superficial etching observed below energy densities of 100 mJ/cm2 is due to desorption of the Sb-oxides stimulated by photolysis. Above this threshold, the remaining Ga oxides are burried into the melted layer. The photolysis of the oxide also stimulates a layer-by-layer oxidation when GaSb is irradiated in air at lower energy densities (1 to 3 mJ/cm2 ).

We have applied Low Energy Ion Scattering(LEIS) to study initial stage of molecular beam epitaxy(MBE), which is highly sensitive to local atomic structures of the substrate surface. By demonstrating the sensitivity of the new monitor to atomic steps on the substrate surface, we demonstrate its usefulness for analyses of dynamical surface defect processes. We observe a characteristic variation of He+ scattering intensity with respect to the incident angles of primary ions to the substrate surface, and also find a correlation among the transition of growth process, the strain at growth interface and the surface flatness.

The development of tools and processes for a stable patterning process must successfully integrate the lithography and etch modules into a workable unit. As lithography becomes increasingly complex, such as in the case of excimer laser DUV photolithography, the link between the two processing steps becomes even more critical. This work characterized some of the challenges of integrating a DUV lithography process with the standard etching modules. The process studied utilized a negative acting photoresist and a spin-on Anti Reflection Coating. Pattern transfer processes were characterized in terms of critical dimension control, contamination concerns and critical dimension repeatability. Further, the effect of critical lithography parameters were examined as to their modulation of post etch profile characteristics and the effect on focus latitude.

We have performed diagnostic measurements and polysilicon etching experiments using a halfwave radio frequency helical resonator (HR) source with a 150 mm ? discharge to develop and characterize this technology for low-pressure, high density plasma processing. This discharge source was applied to submicron, anisotropic etching of polysilicon gates using Cl2 and Cl2 /HBr at low pressure (~ 10-3 torr). A solenoidal magnetic field ~60 G along the discharge tube axis enhances plasma density between the source and wafer by a factor of 3–4 to > 1011 cm-3 in a 1000W discharge. In a Cl2/20% HBr feed gas mixture we obtain >3000 Å/min for undoped polysilicon, vertical profiles, and no proximity effects using -10 Vdc additional bias imposed on the wafer. Selectivities for polysilicon over gate oxide and trilevel resist were 50:1 and 4:1, respectively, with no bias during the overetching step.

While miniatuarization of semiconductors has enabled aluminum wiring pattern dimensions smaller and smaller, this has also given rise to problems such as stress migration and electromigration. The use of copper reportedly suppreses such migration.

The formation process for trench capacitor etching and its mechanisms in single-crystal silicon with a Cl2/SiCl4 reactive plasma using a multi frequency discharge etch reactor is developed. Trenches are etched using a SiO2 mask on wafers with 150 mm diameter. The influence of process gas flow, pressure, rf-power levels, and temperature is investigated revealing relevant process mechanisms. Attention is paid on the uniformity, reproducibility, and long term stability of the process. Determining the process window by varying the process parameters the changes in trench shapes are investigated giving access to the possibility of a sensitive control of the desired trench profile. The trench profiles achieved under our process conditions meet all requirements demanded by the application in advanced production lines.