Presentation + Paper
27 April 2023 Using active asymmetry control and blind source separation to improve the accuracy of after develop overlay measurements
Author Affiliations +
Abstract
During metrology overlay recipe setup typically a wide range of different target designs are present to select from. The main goal of recipe setup is to select the most accurate target type-recipe combination at ADI (after develop inspection) without additional external information that can be used for production on a large set of wafers. We will introduce a method based on blind source separation to disentangle the contributions of target asymmetry and the overlay of the targets. Based on this separation, the most accurate target-recipe combination can be selected. On top of selecting the most accurate target-recipe combination, it is important to stabilize the difference between the overlay on device and the overlay as measured on the target. In order to increase that stability we will introduce advanced algorithms in the ADI measurements that use measured asymmetry parameters to correct for inline target asymmetry variation. We will show a metrology to device matching improvement of up to 40% on product wafers.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jungmin Lee, Doogyu Lee, Eunji Lee, Inbeom Yim, Jeongjin Lee, Seung Yoon Lee, Chan Hwang, Marc Noot, Arno van Leest, Simon Mathijssen, Yao Gao, Seung-Bin Yang, Mi-Yeon Baek, Do-Haeng Lee, Han-Gyeol Park, Jong-Hyuk Yim, Thomas Kim, Ho-Hyuk Lee, Kemal Dahha, Stefan Smith-Meerman, Koen van Witteveen, Elliott McNamara, and Matthew McLaren "Using active asymmetry control and blind source separation to improve the accuracy of after develop overlay measurements", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960H (27 April 2023); https://doi.org/10.1117/12.2658330
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KEYWORDS
Overlay metrology

Semiconducting wafers

Metrology

Matrices

Polarization

Signal processing

Wafer testing

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