Mr. Christopher M. Cork Profile

Christopher M. Cork

Senior Staff Engineer at Synopsys SARL

SPIE Involvement:

Author

Publications (28)

Proceedings Article | 12 April 2013 Paper

An investigation into scalability and compliance for triple patterning with stitches for metal 1 at the 14nm node

Christopher Cork, Alexander Miloslavsky, Paul Friedberg, Gerry Luk-Pat

Proceedings Volume 8683, 868308 (2013) https://doi.org/10.1117/12.2011548

KEYWORDS: Optical lithography, Metals, Photomasks, Double patterning technology, Lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Legal, Network architectures, Fractal analysis

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Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.

Proceedings Article | 13 March 2012 Paper

Edge placement error reduction and ringing effect suppression using model based targeting techniques

Chris Cork, Xiaohai Li, Stephen Jang

Proceedings Volume 8326, 83261U (2012) https://doi.org/10.1117/12.916623

KEYWORDS: Optical proximity correction, Lithographic illumination, Photomasks, Lithography, Surface conduction electron emitter displays, Neodymium, Extreme ultraviolet lithography, Scanners, Image resolution, Optical lithography

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Proceedings Article | 7 March 2012 Open Access

Implications of triple patterning for 14nm node design and patterning

Kevin Lucas, Chris Cork, Bei Yu, Gerard Luk-Pat, Ben Painter, David Pan

Proceedings Volume 8327, 832703 (2012) https://doi.org/10.1117/12.920028

KEYWORDS: Optical lithography, Photomasks, Logic, Lithography, Double patterning technology, Etching, Immersion lithography, Cadmium sulfide, Metals, Dielectrics

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Proceedings Article | 25 September 2010 Paper

Optical proximity correction challenges with highly elliptical contacts

Chris Cork, Levi Barnes, Yang Ping, Xiaohai Li, Stephen Jang

Proceedings Volume 7823, 78233R (2010) https://doi.org/10.1117/12.867247

KEYWORDS: Optical proximity correction, Photomasks, Calibration, Manufacturing, Semiconducting wafers, Tolerancing, Diffraction, Image processing, Critical dimension metrology, Immersion lithography

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The steady march of Moore's law demands ever smaller feature sizes to be printed and Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently pitch doubling techniques has relieved the pressure on CD reduction, which instead of being achieved lithographically are reduced by subsequent etching or chemical interaction with spin-on layers. CD tolerance reductions, however, still need to match the overall design rule shrinkage. The move to immersion lithography, where effective Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction in depth of focus, especially on isolated contacts. To remedy this, RET techniques such as assist feature placement, have been implemented. Certain local placements of assist features and neighboring contacts are observed to result in highly elliptical contacts being printed. In some layouts small changes in the aspect ratio of the contact on the mask leads to strong changes in the aspect ratio of the printed contact, whereas in other layouts the response is very weak. This effect can be described as an aspect ratio MEEF. The latter type of contact can pose a significant challenge to the OPC recipe which is driven by the need to place the printed contour within a small range of distance from target points placed on the midpoint of edges of a nominally square contact. The OPC challenge naturally will be compounded when the target layout is rectangular in the opposite sense to the natural elliptical shape of the printed contact. Approaches to solving this can vary from intervening at the assist feature placement stage, at the possible loss of depth of focus, to accepting a certain degree of ellipticity in the final contour and making the OPC recipe concentrate on minimizing any residual errors. This paper investigates which contact layouts are most challenging, discusses the compromises associated with achieving the correction target and results are shown from a few different approaches to resolving these issues.

Proceedings Article | 10 March 2010 Paper

Suppressing ringing effects from very strong off-axis illumination with novel OPC approaches for low k1 lithography

Chris Cork, Frank Amoroso, Amyn Poonawala, Stephen Jang, Kevin Lucas

Proceedings Volume 7640, 76401C (2010) https://doi.org/10.1117/12.847977

KEYWORDS: Optical proximity correction, Lithographic illumination, Lithography, Photomasks, Image segmentation, Neodymium, Scanners, Optical lithography, Manufacturing, Far-field diffraction

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Proceedings Article | 4 March 2010 Paper

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

Myung-Soo Noh, Beom-Seok Seo, Suk-Joo Lee, Alex Miloslavsky, Christopher Cork, Levi Barnes, Kevin Lucas

Proceedings Volume 7640, 76400S (2010) https://doi.org/10.1117/12.848194

KEYWORDS: Double patterning technology, Optical lithography, Photomasks, Logic, Product engineering, Parallel processing, Electronics, 193nm lithography, Electronic design automation, Resolution enhancement technologies

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Proceedings Article | 30 September 2009 Paper

Parallel processing for pitch splitting decomposition

Levi Barnes, Yong Li, David Wadkins, Steve Biederman, Alex Miloslavsky, Chris Cork

Proceedings Volume 7488, 74882L (2009) https://doi.org/10.1117/12.831396

KEYWORDS: Double patterning technology, Parallel processing, Photomasks, Lithography, Neodymium, Etching, Optical lithography, Lithium, Immersion lithography, Semiconductor manufacturing

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SPIE Journal Paper | 1 July 2009

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Kevin Lucas, Christopher Cork, Alexander Miloslavsky, Gerard Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Gregory Rollins, Vincent Wiaux, Staf Verhaegen

JM3, Vol. 8, Issue 03, 033002, (July 2009) https://doi.org/10.1117/12.10.1117/1.3158061

KEYWORDS: Semiconducting wafers, Double patterning technology, Lithography, Optical lithography, Etching, Photomasks, Optical proximity correction, Metals, Standards development, Critical dimension metrology

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Proceedings Article | 11 May 2009 Paper

Double patterning addressing imaging challenges for near- and sub-k1=0.25 node layouts

Beom-Seok Seo, Dae-Kwon Kang, Myung-Soo Noh, Sung-Ho Lee, Christopher Cork, Gerald LukPat, Alexander Miloslavsky, Xiaohai Li, Kevin Lucas, Sooryong Lee

Proceedings Volume 7379, 73791N (2009) https://doi.org/10.1117/12.824300

KEYWORDS: Double patterning technology, Optical proximity correction, Silicon, Optical lithography, Photomasks, Logic, Etching, Manufacturing, Metals, Lithography

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A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Proceedings Article | 16 March 2009 Paper

Double-patterning-friendly OPC

Xiaohai Li, Gerry Luk-Pat, Chris Cork, Levi Barnes, Kevin Lucas

Proceedings Volume 7274, 727414 (2009) https://doi.org/10.1117/12.815175

KEYWORDS: Optical proximity correction, Photomasks, Etching, Optical lithography, Double patterning technology, Semiconducting wafers, Critical dimension metrology, Model-based design, Printing, Resolution enhancement technologies

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Proceedings Article | 13 March 2009 Paper

Large-scale double-patterning compliant layouts for DP engine and design rule development

Christopher Cork, Kevin Lucas, John Hapli, Herve Raffard, Levi Barnes

Proceedings Volume 7275, 72751K (2009) https://doi.org/10.1117/12.815213

KEYWORDS: Double patterning technology, Metals, Optical lithography, Optical proximity correction, Standards development, Photomasks, Neodymium, Lithium, Field emission displays, Extreme ultraviolet

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Double Patterning is seen as the prime technology to keep Moore's law on path while EUV technology is still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask technology[1], layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a production worthy double patterning engine with highly non-compliant layouts would put unrealistic expectations on that engine and provide metrics with poor applicability for eventual large designs. The true production use-case would be for designs that have at least some significant double patterning compliance already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and complexities were created that were double patterning compliant. To achieve this, a set of standard cells were generated, which individually and in isolation were double patterning compliant, for multiple layers simultaneously. This was done using the automated Standard Cell creation tool Cadabra^TM [4]. To create a full ASIC, however, additional constraints were added to make sure compliance would not be broken across the boundaries between standard cells when placed next to each other [5]. These standard cells were then used to create a variety of double patterning compliant ASICs using iCCompiler^TM to place the cells correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such large datasets. A production worthy double patterning engine is ideally distributable over multiple processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results can be understood together with metrics such as the distribution of the sizes of networks requiring coloring resulting from these designs.

Proceedings Article | 17 October 2008 Paper

Assist feature aware double patterning decomposition

Christopher Cork, Levi Barnes, Gerard Luk-Pat

Proceedings Volume 7122, 712224 (2008) https://doi.org/10.1117/12.801562

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Lithography, Optical lithography, Cadmium, Tolerancing, Scanners, Critical dimension metrology, Etching

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Proceedings Article | 17 October 2008 Paper

Printability verification for double-patterning technology

Gerard Luk-Pat, Petrisor Panaite, Kevin Lucas, Christopher Cork, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 7122, 71220Q (2008) https://doi.org/10.1117/12.801545

KEYWORDS: Etching, Lithography, Printing, Double patterning technology, Optical proximity correction, Critical dimension metrology, Resolution enhancement technologies, Scanning electron microscopy, Bridges, Extreme ultraviolet

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Proceedings Article | 19 May 2008 Paper

Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns

Christopher Cork, Jean-Christophe Madre, Levi Barnes

Proceedings Volume 7028, 702839 (2008) https://doi.org/10.1117/12.793116

KEYWORDS: Optical lithography, Double patterning technology, Photomasks, Etching, Lithography, Electronic design automation, Extreme ultraviolet lithography, Metals, Printing, Manufacturing

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Proceedings Article | 20 March 2008 Paper

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins, Vincent Wiaux, Staf Verhaegen

Proceedings Volume 6924, 692403 (2008) https://doi.org/10.1117/12.778267

KEYWORDS: Semiconducting wafers, Optical lithography, Photomasks, Double patterning technology, Lithography, Etching, Metals, Optical proximity correction, 193nm lithography, Standards development

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Proceedings Article | 19 March 2008 Paper

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

Yuichi Inazuki, Nobuhito Toyama, Takaharu Nagai, Takanori Sutou, Yasutaka Morikawa, Hiroshi Mohri, Naoya Hayashi, Martin Drapeau, Kevin Lucas, Chris Cork

Proceedings Volume 6925, 69251O (2008) https://doi.org/10.1117/12.773291

KEYWORDS: Inspection, Photomasks, Double patterning technology, Optical proximity correction, Lithography, Printing, Lithographic illumination, Binary data, Critical dimension metrology, Logic

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Proceedings Article | 12 March 2008 Paper

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Chris Cork, Brian Ward, Levi Barnes, Ben Painter, Kevin Lucas, Gerry Luk-Pat, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 6925, 69251Q (2008) https://doi.org/10.1117/12.774647

KEYWORDS: Double patterning technology, Manufacturing, Optical lithography, Photomasks, Logic, Optical proximity correction, Ultraviolet radiation, Lithography, Semiconducting wafers, Phase shifts

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Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Proceedings Article | 27 March 2007 Paper

Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

Kevin Lucas, Chris Cork, Jonathan Cobb, Brian Ward, Martin Drapeau, Charlie Zhang, John Allgair, Mike Kling, Mike Rieger

Proceedings Volume 6520, 65200N (2007) https://doi.org/10.1117/12.715166

KEYWORDS: Optical lithography, Optical proximity correction, Error analysis, Resolution enhancement technologies, SRAF, Lithography, OLE for process control, Photomasks, Manufacturing, Metrology

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An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Proceedings Article | 21 March 2007 Paper

Ensuring production-worthy OPC recipes using large test structure arrays

Christopher Cork, Rainer Zimmermann, Xin Mei, Alexander Shahin

Proceedings Volume 6521, 65211D (2007) https://doi.org/10.1117/12.713411

KEYWORDS: Optical proximity correction, Critical dimension metrology, Manufacturing, Lithography, Tolerancing, Photomasks, Design for manufacturability, Product engineering, Semiconductors, Control systems

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The continual shrinking of design rules as the industry follows Moore's Law and the associated need for low k1 processes, have resulted in more layout configurations becoming difficult to print within the required tolerances. OPC recipes have needed to become more complex as tolerances decreased and acceptable corrections harder to find with simple algorithms. With this complexity comes the possibility of coding errors and ensuring the solutions are truly general. OPC Verification tools can check the quality of a correction based on pre-determined specifications for CD variation, line-end pullback and Edge Placement Error and then highlight layout configuration where violations are found. The problem facing a Mask Tape-Out group is that they usually have little control over the Design Styles coming in. Different approaches to eliminating problematic layouts have included highly restrictive Design Rules [1], whereby certain pitches or orientations are disallowed. Now these design rules are either becoming too complex or they overly restrict the designer from benefiting from the reduced pitch of the new node. The tight link between Design and Mask Tape-Out found in Integrated Device Manufacturers [2] (IDMs) i.e. companies that control both design and manufacturing can do much to dictate manufacturing friendly layout styles, and push ownership of problem resolution back to design groups. In fact this has been perceived as such an issue that a new class of products for designers that perform Lithographic Compliance Check on design layout is an emerging technology [3]. In contrast to IDMs, Semiconductor Foundries are presented with a much larger variety of design styles and a set of Fabless customers who generally are less knowledgeable in terms of understanding the impact of their layout on manufacturability and how to correct issues. The robustness requirements of a foundry's OPC correction recipe, therefore needs to be greater than that for an IDM's tape-out group. An OPC correction recipe which gives acceptable verification results, based solely on one customer GDS is clearly not sufficient to guarantee that all future tape-outs from multiple customers will be similarly clean. Ad hoc changes made in reaction to problems seen at verification are risky, while they may solve one particular layout issue on one product there is no guarantee that the problem may simply shift to another configuration on a yet to be manufactured part. The need to re-qualify a recipe over multiple products at each recipe change can easily results in excessive computational requirements. A single layer at an advanced node typically needs overnight runs on a large processor farm. Much of this layout, however, is extremely repetitive, made from a few standard cells placed tens of thousands of times. An alternative and more efficient approach, suggested by this paper as a screening methodology, is to encapsulate the problematic structures into a programmable test structure array. The dimensions of these test structures are parameterized in software such that they can be generated with these dimensions varied over the space of the design rules and conceivable design styles. By verifying the new recipe over these test structures one could more quickly gain confidence that this recipe would be robust over multiple tape-outs. This paper gives some examples of the implementation of this methodology.

Proceedings Article | 20 October 2006 Paper

Accounting for lens aberrations in OPC model calibration

Laurent Depre, Christopher Cork, Martin Drapeau

Proceedings Volume 6349, 63494L (2006) https://doi.org/10.1117/12.686044

KEYWORDS: Calibration, Monochromatic aberrations, Scanners, Optical proximity correction, Data modeling, Reticles, Semiconducting wafers, Critical dimension metrology, Photomasks, Statistical modeling

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Proceedings Article | 15 March 2006 Paper

Calibrating OPC models using asymmetric structures

Laurent Depre, Christopher Cork, Qiliang Yan

Proceedings Volume 6154, 61541P (2006) https://doi.org/10.1117/12.659715

KEYWORDS: Calibration, Data modeling, Statistical modeling, Monochromatic aberrations, Optical proximity correction, 3D modeling, Performance modeling, Process modeling, Critical dimension metrology, Error analysis

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Proceedings Article | 9 November 2005 Paper

Optimal distributed computing resources for mask synthesis and tape-out in production environment: an economic analysis

Chris Cork, Manoj Chacko, Shimon Levi

Proceedings Volume 5992, 59924C (2005) https://doi.org/10.1117/12.637424

KEYWORDS: Photomasks, Optical proximity correction, Silicon, Prototyping, Resolution enhancement technologies, Manufacturing, Metals, Distributed computing, Semiconductors, Data processing

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Proceedings Article | 28 June 2005 Paper

An economic analysis for optimal distributed computing resources for mask synthesis and tape-out in production environment

Chris Cork, Robert Lugg, Manoj Chacko, Shimon Levi

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617132

KEYWORDS: Photomasks, Optical proximity correction, Silicon, Prototyping, Resolution enhancement technologies, Metals, Distributed computing, Semiconductors, Databases

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Proceedings Article | 5 May 2005 Paper

Line end design intent estimation using curves

Chi-Yuan Hung, Gensheng Gao, Steven Zhang, Ze-Xi Deng, Christopher Cork, Lawrence Melvin, Yan Jiang

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.604526

KEYWORDS: Optical proximity correction, Silicon, Lithography, Design for manufacturing, Semiconductors, Photomasks, Logic, Lithographic illumination, Manufacturing, Transistors

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Semiconductor foundries need to have a single, standard mask preparation procedure to deal with the large number of designs they receive. This data is typically of two sorts; the random logic over which they have little control of how the design intent is represented; and cells from dense arrays such as memory, often with design rule violations, whose OPC correction needs to be precisely optimized to achieve best yield and device performance. Occasionally the input data will contain sub-resolvable notches and extensions, which while not violating DRC specifications, would, if filled, result in DRC violations. This may be due to a non DFM aware automated layout tool, or a designer aggressively trying to minimize circuit density. In practice it is worthwhile to clean up these notches to ease OPC correction. Doing this should not result in printability errors as these notches typically represent a more complex curved design intent that cannot be accurately represented due to the restrictions imposed by the limited number of polygon edge directions available for layout. Similarly, memory cell layouts often have significant implied curvature. These may only be corrected properly if the OPC target point is defined precisely for each individual segment. In general, letting the OPC correction engine correct a layout defined by a realistic, curved target shape gives better quality corrections with greater process window. The challenge for the OPC engineer working in a foundry is therefore to determine a clean-up methodology for incoming data and to correctly apply the design intent, where necessary, from the original pre-cleanup data. A programmable OPC engine gives the user flexibility in optimizing the set of rules embedded in the OPC cleanup and correction recipes. These embed within them the algorithms to interpret the rounding on the desired silicon image not only for line-ends and corners of random logic but also the more complex curved silicon images and tolerances required by memory cells.

Proceedings Article | 6 December 2004 Paper

Maintaining lithographic quality during OPC for low-k1 and MEEF processes constrained by mask dimensional rules

Christopher Cork, Lawrence Melvin, Michael Miller, Robert Lugg, Michael Rieger

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568550

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Image segmentation, Silicon, Model-based design, Mask making, Semiconducting wafers, Resolution enhancement technologies, Transistors

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Proceedings Article | 20 August 2004 Paper

Model-based interpretation filtering for complex two-dimensional layout features

Lawrence Melvin, James Shiely, Christopher Cork, Michael Rieger

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557742

KEYWORDS: Model-based design, Optical proximity correction, Process modeling, Detection and tracking algorithms, Data modeling, Optical lithography, Image processing, Photoresist materials, Performance modeling, Data processing

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Proceedings Article | 3 May 2004 Paper

Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent

Christopher Cork, Pratheep Balasingam, Sonya Sandvik, Bill Kielhorn, Michael Rieger

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.538047

KEYWORDS: Optical proximity correction, Critical dimension metrology, Photomasks, Silicon, Mathematical modeling, Transistors, Semiconducting wafers, Diffusion, Model-based design, Image processing

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Proceedings Article | 22 May 1995 Paper

Near and sub-half-micrometer geometry SEM metrology requirements for good process control

Christopher Cork, Paolo Canestrari, Paolo De Natale, Mauro Vasconi

Proceedings Volume 2439, (1995) https://doi.org/10.1117/12.209238

KEYWORDS: Process control, Metrology, Scanning electron microscopy, Etching, Cadmium, Visibility, Lithography, Metals, Semiconducting wafers, Oxides

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