Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.
EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps.
In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.
EUV (extreme ultraviolet) lithography has recently begun to be applied to semiconductor mass production, and it is expected that more layers will be applied in the future. In particular, the adoption of EUV is a great advantage in that the number of masks required for ArF immersion lithography can be reduced, which can reduce not only the cost but also the risk of EPE (edge placement error) due to superposition. However, the pattern defects of EUV lithography is still issue, and its high resolution performance has not been fully exploited. In order to further pattern shrink of semiconductors in the future, a major issue is how to reduce these defects.
In this report, we introduce the latest approach for mitigation the defects of EUV lithography patterns. The defects are confirmed not only ADI (after development inspection) but also AEI (after etch inspection).
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