One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. The traditional development process might be insufficient to achieve the requirements of ultra-high-resolution features with low defect levels. The aim of this paper is to establish a process to achieve a good roughness, a low defectivity at a low EUV dose, and capability for extremely-high-resolution for high numerical aperture (NA) and hyper-NA EUV lithography. A new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR). ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient (higher exposure latitude (EL)) and reducing scums (fewer bridge defects). This new development method can also keep the resist profile vertical to mitigate the break defects. The performances of the conventional development and ESPERT™ were evaluated and compared using 0.33 NA EUV, 0.5 NA EUV, and electron beam (EB) exposures, for all line-space (LS), contact hole (CH), and pillar (PL) patterns. Using 0.33 NA EUV scanners on LS patterns, both bridge and break defects were confirmed to be reduced for all 32-nm-pitch, 28-nm-pitch, 26-nm-pitch LS patterns while reducing the EUV dose to size (DtS). In the electrical yield (1 meter length) test of breaks/bridges of 26-nm pitch structures, ESPERT™ reduced EUV dose while its combo yield was almost 100% over a wide dose range of 20mJ/cm². For CH patterns, in the case of 32-nm-pitch AEI (after etch inspection), EL was increased 7.5% up to 22.5%, while failure free latitude (FFL) was widened from 1-nm to 4-nm. A 16-nm-pitch LS pattern was successfully printed with 0.5 NA tool, while a 16-nm-pitch PL and an 18-nm-pitch CH patterns were also achieved with an EB lithography by ESPERT™. With ESPERT™, there was no pillar collapse observed for 12-nm half-pitch PL by 0.5 NA and 8-nm half-pitch PL by EB. With all the advantages of having a high exposure sensitivity, a low defectivity, and an extremely-high-resolution capability, this advanced development method is expected be a solution for high-NA EUV towards hyper-NA EUV lithography.
Resolution, line edge roughness (LER) and sensitivity (RLS) and defectivity are the well-known critical issues of extreme ultraviolet (EUV) lithography. To break the RLS triangle, metal oxide resist (MOR) is a promising candidate. However, further improvement of MOR process is required for high volume manufacturing to maintain low defectivity. In this paper, conventional and new processes for MOR pitch 32 nm line and space (L/S) and 36 nm pillar patterns was investigated. This new process was able to perform good sensitivity without degrading roughness. In addition, further optimization for underlayer and developer process could mitigate pattern collapses. MOR treatment was evaluated as another technique for roughness improvement. At last, bottom scum defect would be reduced by new process.
EUV (extreme ultraviolet) lithography has been introduced in high volume manufacturing in 2019 and continuous improvements have allowed to push the lithographic performance to the limits of 0.33 NA single exposure. However, stochastic failures, pattern roughness and local critical dimension uniformity (LCDU) are still major challenges that need to be addressed to maintain node shrinkage and improve yield. Together with pitch downscaling, photoresist thickness is decreasing to prevent pattern collapse. A lower depth of focus is also expected with high NA EUV which might even thin further down the resist layer. Being able to transfer the patterns with good fidelity is therefore getting very challenging because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. A co-optimization of lithography processes, underlayers coating and etch processes is essential to further support the EUV patterning extension.
In this report, recently developed hardware and process solutions to stretch the limits of EUV patterning will be presented. The latest performance for both chemically amplified resists (CAR) and metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.
In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.
Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.
This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination mitigation, while keeping our high standard of CDU. The new bake oven was introduced in our coater and developer and evaluated using line/space patterns. As described in the results, exceptional CD uniformity was realized while exceeding the metal contamination specification. The new plate design also enabled a 30% reduction in dose-to-size without degradation of CDU when applying higher PEB temperature. Another challenge for the DRAM application in particular is pattern collapse as applied to pillar patterns. By optimization of several parameters, the pattern collapse margin extended the minimum CD by 13.8%. The result was achieved with a combination of SiC in place of SOG for under layer, thinner resist film thickness and a modified resist material, MOR-B. Finally, to achieve target yield performance, defectivity reduction is also an important task towards MOR application. An integrated approach is needed to realize scum free patterning because if metal residuals remain in the open space, they can cause yield-killing defects. By analyzing possible root causes of defect sources, we attempt to eliminate etch-masking scum layer present after conventional developer processing. By applying a post develop rinse including novel hardware for defect reduction, bridge defects were reduced up to 19% with new the technology.
The application of metal-oxide resist (MOR) for mass production is highly expected since MOR has an advantage of higher resolution. However, the metal components itself has a high risks of metal contamination and the defects based on metal components. Therefore, control of defects is more important than conventional chemically amplified resist (CAR). In this paper, reduction of defect densities are examined by latest technologies in the coater/developer. As results, on pillar pattern, many fall-on and scum defects were observed and majority of them were transferred to underlayer by etching process. In order to reduce the fall-on and the scum defects, three possible solutions were proposed. First, the latest resist supply system was designed for MOR. In addition, particles emitted from the latest supply system was reduced compared to the conventional system. Second, improvement of purity of the developer solution contributed to the reduction of fall-on particles. Third, application of the optimized rinse after development reduced 12% of the scum defect on the pillar pattern after lithography. It contributed to 19% (single bridge) and 18% (multi bridge) reduction after etching process. Furthermore, the optimized rinse reduced the single bridges on the line and space (L/S) pattern by 14% after etching process. These proposed three technologies are expected to be utilized for high volume manufacturing.
EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps.
In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.
Extreme ultraviolet (EUV) lithography has been begun high volume manufacturing (HVM). To allow for robust processing, both CAR and novel metal oxide resist (MOR) materials are needed, but they each come with unique challenges specific to the layer being printed. CAR resist shows good capability for CH printing and pattern transfer. However, specific processing techniques for the pattern transfer is required to mitigate LCDU issues. Additionally CAR L/S printing shows robust capability at 18nm HP, but when approaching 16nm HP, the defect process window is impacted by collapse and bridging. For ultimate resolution, novel materials such as MOR have been demonstrated but sensitivities of the materials for CD stability and defectivity need to be mitigated. TOKYO ELECTRON investigates ways to reduce these risks with a novel approach for coating process, post exposure bake, and developing sequence.
This paper reports technologies to improve CDU, PW, and defectivity. In addition, we report solutions of solving metal contamination risk for MOR while maintaining productivity.
Inpria has pioneered the development of high-resolution metal oxide (MOx) photoresists designed to unlock the full potential of EUV lithography. In addition to resolution, LWR, and sensitivity to enable advanced process nodes, there are also stringent defectivity requirements that must be realized for any resist system. We will review advances in post-etch defectivity based on: resist design and formulation, track process design, developer design, and etch optimization. We will present data supporting each of these topics quantifying the defect impact and will describe improvement strategies to take full advantage of such MOx resist systems.
EUV (extreme ultraviolet) lithography has recently begun to be applied to semiconductor mass production, and it is expected that more layers will be applied in the future. In particular, the adoption of EUV is a great advantage in that the number of masks required for ArF immersion lithography can be reduced, which can reduce not only the cost but also the risk of EPE (edge placement error) due to superposition. However, the pattern defects of EUV lithography is still issue, and its high resolution performance has not been fully exploited. In order to further pattern shrink of semiconductors in the future, a major issue is how to reduce these defects.
In this report, we introduce the latest approach for mitigation the defects of EUV lithography patterns. The defects are confirmed not only ADI (after development inspection) but also AEI (after etch inspection).
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.