In today’s advanced semiconductor industry with the multitude of new products and device requirements, lithography process changes are inevitable and expected due to tighter overlay specifications and the increasing influence of process effects. To minimize the overlay impact from the wafer-to-wafer and lot-to-lot variation, lithography engineers often need to adjust wafer alignment and overlay strategies to optimize product yield. Overlay simulation methods are often used to estimate if new alignment and/or overlay strategies can help achieve better overlay performance. By removing the old corrections from the original alignment and overlay data, and then applying new corrections, the overlay performance can be readily predicted, saving significant time. However, available software suites only simulate the current layer overlay. Overlay risks would therefore remain on subsequent layers without an effective simulation method to predict the impact resulting from changes to the alignment and/or overlay strategies on the current layer. In our study, we demonstrate a new method to simulate the overlay performance on the subsequent layers by re-calculating the current layer exposure grid. Our dataset has 3 layers: L0, L1, and L2. On L1 (current layer), we apply a new alignment model and overlay control strategy with a feedforward solution. Then, we re-calculate the exposure grid to generate a new (virtual) alignment and overlay dataset for L2 (following layer). Finally, we estimate the overlay impact on L2 with the new alignment and overlay dataset and summarize the benefits of this new cross-layer overlay simulation method.
Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. Using information from non-lithography process steps can unleash overlay improvement potential.1 The challenge is to find intra-wafer signatures by measuring planar distortion. Several previous applications showed that using exposure tool wafer alignment data can improve overlay performance.2 With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this paper, the capability to do this is evaluated in a feasibility study.
It was proven that higher order intra-field alignment data modeling and correction has the potential to improve overlay performance by correcting reticle heating and lens heating effects intra-wafer and wafer- to-wafer.1 But there were also challenges shown that needed further investigation. As the alignment measurement is done on a coordinate system with absolute positions, the modeled iHOPC values might be high. A suitable method needs to be developed to distinguish between tool-to-tool offsets, process influence and layer-to-layer tool stack effect. In this paper we will take the next step and evaluate the overlay improvement potential by using intra-field alignment data in an overlay feed-forward simulation. An overlay run-to-run simulation is afterwards performed to estimate the optimization potential. To simulate higher order intra-field overlay, dense alignment data is needed. Facing the challenge of optimizing the number of measured marks but not losing relevant information, an intra-field alignment mark sampling optimization is done to find the best compromise between throughput and overlay accuracy.
Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
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