Silicon photonics platforms leveraging 300mm manufacturing fabrication plants is a growing sector. This trend will continue as the demand for energy efficient data centers, advanced quantum computing architectures and AR/VR drive demand forward. GlobalFoundries is at the forefront of advanced photonics platforms implementation and have recently announced it is collaborating with industry leaders to deliver innovative, unique, feature-rich solutions to solve some of the biggest challenges facing data centers today. In this paper we investigate the impact of process manufacturing techniques typically used in advanced logic and memory on photonics waveguides uniformity improvement and smoothing. Some focus will be placed on the patterning process itself investigating effects of plasma VUV cure, direct current superposition and area selective deposition on resist for downstream line edge roughness and line width roughness impact. We will also review impact of silicon nitride film uniformity and top roughness smoothing on final waveguide optical performance. While silicon photonics features are much larger than logic features, process requirements to achieve required optical performance are stringent and will require innovative solutions to continue driving down optical losses.
This conference presentation was prepared for the Advanced Etch Technology and Process Integration for Nanopatterning XII conference at SPIE Advanced Lithography + Patterning 2023.
As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.
As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure
to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass
processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction
of new process enablers that allow the simultaneous support of flexible foundry-oriented ground rules alongside highperformance
technology, while also migrating to a single-pass patterning process. The incorporation of device based
performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of
material innovation for improved resolution and CD shrink along with novel data preparation flows utilizing aggressive
strategies for SRAF insertion and retargeting.
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