Mr. Ronald Otten Profile

Ronald Otten

at ASML Netherlands BV

SPIE Involvement:

Author

Publications (6)

Proceedings Article | 21 November 2023 Presentation + Paper

New technique for measuring free-form wafer shape to enable wafer distortion predictions

Kiril Ivanov Kurteva, Guillermo Castro Luis, Juan Trujillo-Sevilla, Jan Gaudestad, Richard van Haren, Leon van Dijk, Ronald Otten

Proceedings Volume 12750, 127500H (2023) https://doi.org/10.1117/12.2687605

KEYWORDS: Semiconducting wafers, Optical alignment, Silicon, Alignment modeling, Data acquisition, Coating stress, Wavefronts, Wafer-level optics, Scanners, Optical parametric oscillators

Read Abstract +

On product overlay (OPO) is one of the most critical parameters for continued scaling according to Moore’s law. Besides the lithography scanner, also non-lithography processes contribute to the OPO performance. For example, processes like etching and thin film deposition can introduce stress, or stress changes, in the thin films on top of the silicon wafers. In general, the scanner Higher Order Wafer Alignment model up to 3rd order (HOWA3) has proven to be adequate to correct for most process-induced wafer distortions. This model is typically used with 28 wafer alignment marks placed across the wafer to correct for more global stress-induced distortions. It is evident that if the stress variation manifests itself on shorter length scales, either more alignment marks are needed in combination with a more sophisticated wafer alignment model, or an alternative measurement of the wafer distortion is required. A viable alternative to characterize local wafer deformations is by measuring the free-form wafer-shape change due to processing. In case the wafer-shape change can be translated into a wafer distortion map, it can be complementary to what is already captured by the scanner wafer alignment model. In this paper, we would like to explore this functionality that is based on a new method to measure the free-form wafer shape. Wave Front Phase Imaging (WFPI) generates the wafer shape by registering the intensity of the light reflected off the patterned or blank silicon wafer surface at two different locations along the optical path. The wafer is held vertically to allow for the free-form wafer shape to be measured without being affected by gravity. We show data acquired on specialty made silicon wafers using a WFPI lab tool that acquired 16.3 million data points on a 300mm wafer with 65μm spatial resolution. The obtained free-form wafer-shape measurements are fed into existing prediction models and the resulting wafer distortion maps are compared with scanner measurements.

Proceedings Article | 29 May 2023 Presentation + Paper

Track integrated backside cleaning solution: impact of backside contamination on printing distortions

Andreia Santos, Wesley Zanders, Elke Caron, Masahiko Harumoto, Jelle Vandereyken, Jan Hermans, Vincent Truffert, Sandip Halder, Ronald Otten, Leon van Dijk, Richard van Haren

Proceedings Volume 12498, 1249809 (2023) https://doi.org/10.1117/12.2658418

KEYWORDS: Semiconducting wafers, Particles, Contamination, Extreme ultraviolet lithography, Scanners, Displays, Extreme ultraviolet, Printing, Industry, Optical lithography

Read Abstract +

Proceedings Article | 27 April 2023 Poster + Paper

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Viorel Balan, Florent Michel, Ivanie Mendes, Celine Lapeyre, Lionel Vignoud, Ronald Otten, Orion Mouraille, Leon van Dijk, Blandine Minghetti, Jerome Depre, Richard van Haren

Proceedings Volume 12496, 1249633 (2023) https://doi.org/10.1117/12.2658296

KEYWORDS: Annealing, Semiconducting wafers, Metrology, Distortion, Overlay metrology, Deformation, Chemical mechanical planarization, Silicon, Optical interferometry, Manufacturing

Read Abstract +

Proceedings Article | 29 August 2019 Paper

Detection and mitigation of furnace anneal induced distortions at the wafer edge

Leon van Dijk, Anne-Laure Charley, Maarten Stokhof, Ronald Otten, Sven Van Elshocht, Bert Jongbloed, Philippe Leray, Richard van Haren

Proceedings Volume 11177, 1117714 (2019) https://doi.org/10.1117/12.2535636

KEYWORDS: Semiconducting wafers, Scanners, Optical alignment, Overlay metrology, Metrology, Annealing

Read Abstract +

Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.

Proceedings Article | 26 March 2019 Paper

Intra-field stress impact on global wafer deformation

Richard van Haren, Ronald Otten, Subodh Singh, Amandev Singh, Leon van Dijk, David Owen, Doug Anberg, Jeffrey Mileham, Yajun Gu, Jan Hermans

Proceedings Volume 10959, 109591I (2019) https://doi.org/10.1117/12.2515391

KEYWORDS: Semiconducting wafers, Distortion, Scanners, Optical alignment, Silicon, Overlay metrology, Etching, Performance modeling, Silicon films, Annealing

Read Abstract +

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer alignment functionality addresses the random part that is varying from wafer-to-wafer.

In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years.

In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.

Proceedings Article | 12 June 2018 Paper

Intra-field mask-to-mask overlay, separating the mask writing from the dynamic pellicle contribution

Richard van Haren, Steffen Steinert, Orion Mouraille, Koen D’havé, Leon van Dijk, Ronald Otten, Dirk Beyer

Proceedings Volume 10807, 108070K (2018) https://doi.org/10.1117/12.2500086

KEYWORDS: Pellicles, Overlay metrology, Reticles, Scanners, Photomasks, Image registration, Semiconducting wafers, Optical alignment, Distortion, Deep ultraviolet

Read Abstract +

The number of masks required to produce an integrated circuit has increased tremendously over the past years. The main reason for this is that a single layer mask exposure and etch was no longer sufficient to meet the required pattern density. A solution was found in the application of multi-patterning steps, including multiple masks, before the final pattern is transferred into the underlying substrate. Consequently, the mask-to-mask contribution as part of the overall on-product (intra-layer) overlay budget could not be neglected anymore. While the tight on-product overlay specifications (< 3-nm) were initially only requested for the intra-layer (e.g. multi Litho Etch Litho Etch) overlay performance, recently these tight requirements are also imposed for the layer-to-layer overlay. Recently, we reported on an extensive study in which the mask-to-mask overlay contribution as determined by the PROVE mask registration tool was correlated with actual on-wafer measurements. Two ASML BMMO (Baseliner Matched Machine Overlay) masks were used for this purpose. Initially, no pellicles were mounted onto the masks. An excellent correlation was found between the measurements on the PROVE tool and the on-wafer results reaching R² < 0.96 with an accuracy of 0.58-nm. The accuracy level can be further improved since all underlying contributors were identified. It was concluded that the expected overlay as measured on-wafer can be fully determined by off-line registration measurements only. An important note is that the off-line registration measurements on the PROVE tool are performed in a static mode, while the exposures on an ASML TWINSCANTM are performed in a dynamic (scanning) mode. No impact was observed since both masks were not equipped with a pellicle. One can expect that also for the case where both masks are equipped with a pellicle of the same type, the impact is negligible. The reason for this is that all pellicle induced errors are likely to be the same for both masks in scanning mode and will cancel out in the overlay. However, the correlation between offline mask-to-mask overlay measurements and on-wafer measurements is expected to deteriorate when only one of the masks is equipped with a pellicle. Evidence for this was already found even when we operated the scanner in slow scan mode. In this work, we have extended the study by considering the impact of a pellicle on one of the masks and how it affects the intra-field overlay. As a logical consequence, it will have an impact on the correlation between the mask-to-mask and the on-wafer overlay measurements. An experimental technique has been developed to isolate the main impact of a scanning pellicle. We show that, in addition to the mask-to-mask writing errors, the pellicle induced errors can be characterized as well. We demonstrate that the correlation is restored when the pellicle contribution is removed from the on-wafer overlay measurements. The impact of the pellicle on the intra-field overlay performance should be treated as a separate overlay contributor that needs to be minimized separately. Calibration and scanner correction capabilities are in place to mitigate the pellicle induced overlay errors.

Showing 5 of 6 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years