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Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing
Printability and propagation of stochastic defects through a study of defects programmed on EUV mask
In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.
Accurate identification of process windows can be accomplished using KLA-Tencor’s fixed focus offset conditions and Process window Discovery (PWD) methodology[1]. The PWD methodology makes use of a modulated wafer layout to enable inspection comparing nominal to modulated conditions. KLA-Tencor’s Broadband plasma (BBP) inspection technology is used to compare the nominal conditions to each experimental condition and to identify systematic defects. The identification of systematic defects is enabled by the PWD method by first discovering potential patterns of interest and then generating NanopointTM care areas around every occurrence of the patterns of interest. This allows identification of critical systematic structures that may have the same design intent but do not repeat in the same X,Y locations within a device. This approach maximizes the inspection sensitivity on each structure type, accurately identifies the edge of the process window in focus and dose, and enables study of the sensitivity of fixes process offsets (such as light source bandwidth).
In this study, a tunable DUV light source bandwidth technique and the PWD methodology are used to study the light source E95 bandwidth impact on Metal layer features from an imec 10 nm node logic-type test vehicle.
EPE analysis of sub-N10 BEoL flow with and without fully self-aligned via using Coventor SEMulator3D
High-throughput multi-beam SEM: quantitative analysis of imaging capabilities at IMEC-N10 logic node
In this paper, we propose a new generation of software platform and development infrastructure which can integrate specific metrology business modules. For example, we will show the integration of a chemistry module dedicated to electronics materials like Direct Self Assembly features. We will show a new generation of image analysis algorithms which are able to manage at the same time defect rates, images classifications, CD and roughness measurements with high throughput performances in order to be compatible with HVM. In a second part, we will assess the reliability, the customization of algorithm and the software platform capabilities to follow new specific semiconductor metrology software requirements: flexibility, robustness, high throughput and scalability. Finally, we will demonstrate how such environment has allowed a drastic reduction of data analysis cycle time.
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