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Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield.
In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.
We were able to change the spatial orientation of Silicon nanowires by modifying scanning conditions which effectively controls the amount of charging induced by the SEM. Strong charging, which corresponds to high dose leads to change of silicon wires spatial orientation, they appear straight in SEM top view and tilt image planes. Reducing charging by the means of scan rate increase or lower number of scanned frames saves the silicon wires buckled in their natural state.
Device performance is strongly correlated with Fin geometry causing an urgent need for 3D measurements. New beam tilting capabilities enhance the ability to make 3D measurements in the front-end-of-line (FEOL) of the metal gate FinFET process in manufacturing. We explore these new capabilities for measuring Fin height and build upon the work communicated last year at SPIE1. Furthermore, we extend the application of the tilt beam to the back-end-of-line (BEOL) trench depth measurement and demonstrate its capability in production targeting replacement of the existing Atomic Force Microscope (AFM) measurements by including the height measurement in the existing CDSEM recipe to reduce fab cycle time.
In the BEOL, another increasingly challenging measurement for the traditional CD-SEM is the bottom CD of the self-aligned via (SAV) in a trench first via last (TFVL) process. Due to the extremely high aspect ratio of the structure secondary electron (SE) collection from the via bottom is significantly reduced requiring the use of backscatter electrons (BSE) to increase the relevant image quality. Even with this solution, the resulting images are difficult to measure with advanced technology nodes. We explore new methods to increase measurement robustness and combine this with novel segmentation-based measurement algorithm generated specifically for BSE images. The results will be contrasted with data from previously used methods to quantify the improvement. We also compare the results to electrical test data to evaluate and quantify the measurement performance improvements.
Lastly, according to International Technology Roadmap for Semiconductors (ITRS) from 2013, the overlay 3 sigma requirement will be 3.3 nm in 2015 and 2.9 nm in 2016. Advanced lithography requires overlay measurement in die on features resembling the device geometry. However, current optical overlay measurement is performed in the scribe line on large targets due to optical diffraction limit. In some cases, this limits the usefulness of the measurement since it does not represent the true behavior of the device. We explore using high voltage imaging to help address this urgent need. Novel CD-SEM based overlay targets that optimize the restrictions of process geometry and SEM technique were designed and spread out across the die. Measurements are done on these new targets both after photolithography and etch. Correlation is drawn between the two measurements. These results will also be compared to conventional optical overlay measurement approaches and we will discuss the possibility of using this capability in high volume manufacturing.
To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.
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The course covers advanced concepts for metrology toolset stability and matching. It will cover many critical topics that together maximize fleet performance. This is especially important given the shift to new device architectures (finfet, 3D Flash, DRAM and advanced memory ) that are challenging metrology toolsets in ways not seen before. A number of advanced concepts will be covered. Review best known methods for gauge study analysis and metrics. Appropriately setting up tool control chart limits for long term stability fleet matching based on requirements not historical data. Leveraging real time normalized product data to decrease Mean Time To Detect (MTTD) tool drifts. Recipe portability matching and monitoring to catch other issues that will affect lot cycletime. The concepts discussed are applicable to any metrology toolset such as CD-SEM, overlay, thin film, AFM, etc. and most of these concepts are also applicable to defect toolsets.
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