Dr. John C. Robinson Profile

Dr. John C. Robinson

Senior Principal Scientist

SPIE Involvement:

Conference Program Committee | Symposium Chair | Author | Editor

Area of Expertise:

Metrology , Process Control , Physics , Inspection , Semiconductor Manufacturing , meta optics

Websites:

Personal Website | Company Website

Publications (49)

Proceedings Article | 12 March 2024 Presentation + Paper

End-to-end process control for AR waveguides

John Robinson, Alessandro Vaglio Pret

Proceedings Volume 12913, 129130T (2024) https://doi.org/10.1117/12.2691004

KEYWORDS: Waveguides, Modulation transfer functions, Process control, Augmented reality, Inspection, Metrology

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Proceedings Article | 22 February 2021 Presentation

Welcome and Introduction to SPIE Conference 11611

Ofer Adan, John Robinson

Proceedings Volume 11611, 1161105 (2021) https://doi.org/10.1117/12.2592866

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Proceedings Article | 22 February 2021 Presentation + Paper

The emergence of inline screening for high volume manufacturing

Oreste Donzella, John Robinson, Kara Sherman, Justin Lach, Mike von den Hoff, Barry Saville, Thomas Groos, Alex Lim, David Price, Jay Rathert, Chet Lenox

Proceedings Volume 11611, 1161107 (2021) https://doi.org/10.1117/12.2584770

KEYWORDS: Semiconducting wafers, Reliability, Inspection, Process control, Semiconductors, Manufacturing, Packaging, Machine learning, Silicon carbide, High volume manufacturing

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Proceedings Article | 20 March 2020 Paper

Inline Part Average Testing (I-PAT) for automotive die reliability

John Robinson, Kara Sherman, David Price, Jay Rathert

Proceedings Volume 11325, 113250D (2020) https://doi.org/10.1117/12.2551539

KEYWORDS: Reliability, Inspection, Semiconducting wafers, Semiconductors, Defect inspection

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Semiconductor reliability in applications such as automotive is getting increased attention as design rules shrink to include 1Xnm, semiconductor content per vehicle continues to grow, applications become more critical and reliability requirements tighten. Current automotive requirements stipulate less than one defective part per million (DPPM). Approaches to address reliability include improving design, manufacturing and test. Process control in manufacturing is critical for reliability and includes continuous improvement for reducing process tool defectivity, excursion monitoring of process tools and product lines, golden or best performing tool methods [1], measurement system analysis (MSA) methods and screening. Inline defectivity is known to have an impact on both yield and reliability [2], and defects can impact reliability in one of two ways. Killer defects located in areas that are untested can result in so called Zero- Kilometer failures. In other cases, the same types of defects that cause yield loss can also cause latent reliability failures – the difference being size, location and density. Latent reliability defects become activated after test and can include defect types such as partial bridges, partial opens, and embedded particles. Current reliability engineering relies on outlier detection rules like parametric part average testing (P-PAT) [3], or geographic part average testing (G-PAT), both of which are derived from end-of-line screening data, which is based solely on electrical test data [4]. Inline Part Average Testing (I-PAT™) is enabled by multi-channel high-speed LED scanning inspection technology and offers an opportunity to apply fab data to reliability engineering. Defect inspection results are analyzed with machine learning (ML) to weigh the defectivity and create a die-level defectivity metric allowing the statistical identification of die which are a high reliability risk [5, 6]. Two case studies are described. The first case is a feasibility study based on historical fab defectivity data and includes a sample of ~250,000 die, with eight inline defect inspections per wafer, including four front end of line (FEOL) and four back end of line (BEOL), on a high sensitivity broadband inspection system [7, 8]. Each defect is assigned a weight based on its impact to various “ground truth” indicators. The combined impact of all defects in a given die stacked across all inspections is aggregated into a die-level metric. Plotting the die-level I-PAT metrics for all the die as a Pareto chart allows outliers to be identified using accepted statistical methods [9]. I-PAT metrics can then be correlated to electrical wafer sort (EWS) yield or fallout rate, specific wafer-sort bins, EWS parametric test performance and post burn-in electrical test. Of key importance is that wafer test was not used to train the I-PAT model, and therefore this method is an independent validation of latent reliability. The second case study focuses on production screening feasibility with multi-channel high-speed LED scanning, and addresses overkill, or the over inking of potentially good die based on inline defectivity, which is a critical challenge that must be overcome for production implementation [10]. Using inspection enabled by high speed LED scanning technology, die screening is a critical component of a comprehensive automotive Zero Defect program. Applications include early detection of fab excursions, feedback for continuous improvement of inline defectivity, feedforward to optimize electrical test methods and screening of die containing possible latent reliability defects. The I-PAT methodology can be used to enhance standard end-of-line outlier detection rules such as P-PAT [3], which is based solely on parametric testing.

Proceedings Article | 26 March 2019 Paper

Improved accuracy and robustness for advanced DRAM with tunable multi-wavelength imaging and scatterometry overlay metrology

Honggoo Lee, Sangjun Han, Minhyung Hong, Jieun Lee, Dongyoung Lee, Ahlin Choi, Chanha Park, Dohwa Lee, Seongjae Lee, Jungtae Lee, Jeongpyo Lee, DongSub Choi, Sanghuck Jeon, Zephyr Liu, Hao Mei, Tal Marciano, Eitan Hajaj, Lilach Saltoun, Dana Klein, Eran Amit, Anna Golotsvan, Wayne Zhou, Eitan Herzel, Roie Volkovich, John Robinson

Proceedings Volume 10959, 109591E (2019) https://doi.org/10.1117/12.2515015

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scatterometry, Wafer-level optics, Manufacturing, Quality measurement, Imaging systems, Scanning electron microscopy, Diffractive optical elements

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Overlay process control is a critical aspect of integrated circuit manufacturing. Advanced DRAM manufacturing overlay error budget approaches the sub-2nm threshold, including all sources of overlay error: litho processing, non-litho processing, metrology error, etc. Overlay measurement quality, both for accuracy and robustness, depends on the metrology system and its recipe setup. The optimal configuration depends on the layer and materials involved. Increased flexibility of metrology setup is of paramount importance, paired with improved methods of recipe optimization.

Both optical image-based overlay (IBO) and scatterometry diffraction overlay (SCOL®) are necessary tools for overlay control. For some devices and layers IBO provides the best accuracy and robustness, while on others SCOL provides optimum metrology. Historically, wavelength selection was limited to discrete wavelengths and at only a single wavelength. At advanced nodes IBO and SCOL require wavelength tunability and multiple wavelengths to optimize accuracy and robustness, as well as options for polarization and numerical aperture (NA). In previous studies^1,2,3 we investigated wavelength tunability analysis with landscape analysis, using analytic techniques to determine the optimal setup. In this report we show advancements in the landscape analysis technique for IBO through both focus and wavelength, and comparisons to SCOL. A key advantage of imaging is the ability to optimize wavelength on a per-layer basis. This can be a benefit for EUV layers in combination with those of 193i, for example, as well as other applications such as thick 3D NAND layers. The goal is to make accurate and robust overlay metrology that is immune from process stack variations, and to provide metrics that indicate the quality of metrology performance. Through both simulation and on-wafer advanced DRAM measurements, we show quantitative benefits of accuracy and robustness to process stack variability for IBO and SCOL applications.

Methodologies described in this work can be achieved using Archer™ overlay metrology systems, ATL™ overlay metrology systems, and 5D Analyzer® advanced data analysis and patterning control solution.

SPIE Journal Paper | 30 November 2018 Open Access

Special Section Guest Editorial: Control of Integrated Circuit Patterning Variance, Part 3: Pattern Roughness, Local Uniformity, and Stochastic Defects

John C. Robinson, Tim Brunner, Gian Lorusso

JM3, Vol. 17, Issue 04, 041000, (November 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041000

KEYWORDS: Stochastic processes, Optical lithography, Integrated circuits, Line edge roughness, Extreme ultraviolet lithography, Line width roughness, Metrology, Critical dimension metrology, Photomasks, Semiconducting wafers

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Proceedings Article | 27 April 2018 Paper

Spectral tunability for accuracy, robustness, and resilience

Einat Peled, Eran Amit, Yuval Lamhot, Alexander Svizher, Dana Klein, Anat Marchelli, Roie Volkovich, Tal Yaziv, Aaron Cheng, Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyoung Kim, Jieun Lee, Dongyoung Lee, Eungryong Oh, Ahlin Choi, DongSub Choi, DoHwa Lee, Sanghuck Jeon, Jungtae Lee, Seongjae Lee, Zephyr Liu, Jeongpyo Lee, John Robinson

Proceedings Volume 10585, 105850S (2018) https://doi.org/10.1117/12.2300507

KEYWORDS: Metrology, Semiconducting wafers, Laser scattering, Laser metrology, Overlay metrology, Quality measurement, Scatterometry, Apodization, Polarization, Image quality

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In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups are suitable for the metrology method as different setups can yield significantly different performance in terms of the accuracy and robustness of the reported OVL values. Finding an optimal measurement setup requires great flexibility in measurement, to allow for high-resolution landscape mapping (mapping the dependence of OVL, other metrics, and details of pupil images on measurement setup). This can then be followed by a method for analyzing the landscape and selecting an accurate and robust measurement setup. The selection of an optimal measurement setup is complicated by the sensitivity of metrology to variations in the fabrication process (process variations) such as variations in layer thickness or in the properties of target symmetry. The metrology landscape changes with process variations and maintaining optimal performance might require continuous adjustments of the measurement setup. Here we present a method for the selection and adjustment of an optimal measurement setup. First, the landscape is measured and analyzed to calculate theory-based accurate OVL values as well as quality metrics which depend on details of the pupil image. These OVL values and metrics are then used as an internal ruler (“self-reference”), effectively eliminating the need for an external reference such as CD-SEM. Finally, an optimal measurement setup is selected by choosing a setup which yields the same OVL values as the self-reference and is also robust to small changes in the landscape. We present measurements which show how a SCOL landscape changes within wafer, wafer to wafer, and lot to lot with intentionally designed process variations between. In this case the process variations cause large shifts in the SCOL landscape and it is not possible to find a common optimal measurement setup for all wafers. To deal with such process variations we adjust the measurement setup as needed. Initially an optimal setup is chosen based on the first wafer. For subsequent wafers the process stability is continuously monitored. Once large process variations are detected the landscape information is used for selecting a new measurement setup, thereby maintaining optimal accuracy and robustness. Methods described in this work are enabled by the ATL (Accurate Tunable Laser) scatterometry-based overlay metrology system.

Proceedings Article | 13 March 2018 Presentation + Paper

In-cell overlay metrology by using optical metrology tool

Honggoo Lee , Sangjun Han, Minhyung Hong, Seungyoung Kim, Jieun Lee, DongYoung Lee, Eungryong Oh, Ahlin Choi, Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John Robinson

Proceedings Volume 10585, 105851D (2018) https://doi.org/10.1117/12.2300946

KEYWORDS: Semiconducting wafers, Overlay metrology, Model-based design, Metrology, Diffractive optical elements, Etching, Process modeling, Process control, Optical imaging, Optical metrology

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Proceedings Article | 13 March 2018 Paper

Clean focus, dose and CD metrology for CD uniformity improvement

Honggoo Lee , Sangjun Han, Minhyung Hong, Seungyoung Kim, Jieun Lee, DongYoung Lee, Eungryong Oh, Ahlin Choi, Nakyoon Kim, John Robinson, Markus Mengel , Rovira Pablo , Sungchul Yoo, Raphael Getin, Dongsub Choi, Sanghuck Jeon

Proceedings Volume 10585, 105852A (2018) https://doi.org/10.1117/12.2299976

KEYWORDS: Semiconducting wafers, Metrology, Critical dimension metrology, Scanners, Process control, Modulation, Scatterometry, Finite element methods, Signal to noise ratio, Single crystal X-ray diffraction

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Proceedings Article | 28 March 2017 Presentation + Paper

Patterned wafer geometry grouping for improved overlay control

Honggoo Lee, Sangjun Han, Jaeson Woo, Junbeom Park, Changrock Song, Fatima Anis, Pradeep Vukkadala, Sanghuck Jeon, DongSub Choi, Kevin Huang, Hoyoung Heo, Mark Smith, John Robinson

Proceedings Volume 10145, 101450O (2017) https://doi.org/10.1117/12.2257834

KEYWORDS: Semiconducting wafers, Overlay metrology, Metrology, Process control, Optical lithography, Semiconductor manufacturing, Control systems, Inspection, Tolerancing, Manufacturing, Seaborgium, Semiconductors, Optical alignment, Principal component analysis

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Proceedings Article | 28 March 2017 Presentation + Paper

High-volume manufacturing device overlay process control

Honggoo Lee, Sangjun Han, Jaeson Woo, DongYoung Lee, ChangRock Song, Hoyoung Heo, Irina Brinster, DongSub Choi, John Robinson

Proceedings Volume 10145, 101450D (2017) https://doi.org/10.1117/12.2257836

KEYWORDS: Overlay metrology, Process control, Metrology, Scanning electron microscopy, Inspection, Control systems, High volume manufacturing, Semiconductor manufacturing, Optical inspection, Optics manufacturing, Semiconducting wafers, Data modeling, Scanners

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Proceedings Article | 18 March 2016 Paper

Application of overlay modeling and control with Zernike polynomials in an HVM environment

JaeWuk Ju, MinGyu Kim, JuHan Lee, Jeremy Nabeth, Sanghuck Jeon, Hoyoung Heo, John Robinson, Bill Pierson

Proceedings Volume 9778, 977825 (2016) https://doi.org/10.1117/12.2219739

KEYWORDS: Overlay metrology, Zernike polynomials, Process control, Yield improvement, Metrology, Scanners, Image processing, Optical lithography, Control systems, Semiconducting wafers, High volume manufacturing, Data modeling

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Proceedings Article | 18 March 2016 Paper

Advanced overlay: sampling and modeling for optimized run-to-run control

Lokesh Subramany, WoongJae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Karsten Gutjahr, DongSuk Park, Patrick Snow, Miguel Garcia-Medina, Lipkong Yap, Onur Nihat Demirer, Bill Pierson, John Robinson

Proceedings Volume 9778, 97782K (2016) https://doi.org/10.1117/12.2218729

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metrology, Process control, Scanners, Mathematical modeling, High volume manufacturing

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In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Proceedings Article | 18 March 2016 Paper

Device overlay method for high volume manufacturing

Honggoo Lee, Sangjun Han, Youngsik Kim, Myoungsoo Kim, Hoyoung Heo, Sanghuck Jeon, DongSub Choi, Jeremy Nabeth, Irina Brinster, Bill Pierson, John Robinson

Proceedings Volume 9778, 97781F (2016) https://doi.org/10.1117/12.2219701

KEYWORDS: Overlay metrology, Scanning electron microscopy, Metrology, Inspection, High volume manufacturing, Image processing, Process control, Optical lithography, Control systems, Optical metrology, Semiconducting wafers, Data modeling, Transparency

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Proceedings Article | 19 March 2015 Paper

High order overlay modeling and APC simulation with Zernike-Legendre polynomials

JawWuk Ju, MinGyu Kim, JuHan Lee, Stuart Sherwin, George Hoo, DongSub Choi, Dohwa Lee, Sanghuck Jeon, Kangsan Lee, David Tien, Bill Pierson, John Robinson, Ady Levy, Mark Smith

Proceedings Volume 9424, 94241Y (2015) https://doi.org/10.1117/12.2085074

KEYWORDS: Semiconducting wafers, Overlay metrology, Data modeling, Scanners, Zernike polynomials, Process control, Statistical modeling, Feedback control, Mathematical modeling, Performance modeling

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Feedback control of overlay errors to the scanner is a well-established technique in semiconductor manufacturing [1]. Typically, overlay errors are measured, and then modeled by least-squares fitting to an overlay model. Overlay models are typically Cartesian polynomial functions of position within the wafer (X_w, Y_w), and of position within the field (X_f, Y_f). The coefficients from the data fit can then be fed back to the scanner to reduce overlay errors in future wafer exposures, usually via a historically weighted moving average. In this study, rather than using the standard Cartesian formulation, we examine overlay models using Zernike polynomials to represent the wafer-level terms, and Legendre polynomials to represent the field-level terms. Zernike and Legendre polynomials can be selected to have the same fitting capability as standard polynomials (e.g., second order in X and Y, or third order in X and Y). However, Zernike polynomials have the additional property of being orthogonal over the unit disk, which makes them appropriate for the wafer-level model, and Legendre polynomials are orthogonal over the unit square, which makes them appropriate for the field-level model. We show several benefits of Zernike/Legendre-based models in this investigation in an Advanced Process Control (APC) simulation using highly-sampled fab data. First, the orthogonality property leads to less interaction between the terms, which makes the lot-to-lot variation in the fitted coefficients smaller than when standard polynomials are used. Second, the fitting process itself is less coupled – fitting to a lower-order model, and then fitting the residuals to a higher order model gives very similar results as fitting all of the terms at once. This property makes fitting techniques such as dual pass or cascading [2] unnecessary, and greatly simplifies the options available for the model recipe. The Zernike/Legendre basis gives overlay performance (mean plus 3 sigma of the residuals) that is the same as standard Cartesian polynomials, but with stability similar to the dual-pass recipe. Finally, we show that these properties are intimately tied to the sample plan on the wafer, and that the model type and sampling must be considered at the same time to demonstrate the benefits of an orthogonal set of functions.

Proceedings Article | 19 March 2015 Paper

HVM capabilities of CPE run-to-run overlay control

Lokesh Subramany, Woong Jae Chung, Karsten Gutjahr, Miguel Garcia-Medina, Christian Sparka, Lipkong Yap, Onur Demirer, Ramkumar Karur-Shanmugam, Brent Riggs, Vidya Ramanathan, John Robinson, Bill Pierson

Proceedings Volume 9424, 94241V (2015) https://doi.org/10.1117/12.2190852

KEYWORDS: Semiconducting wafers, Overlay metrology, Control systems, Optical parametric oscillators, Scanners, Process control, High volume manufacturing, Metrology, Yield improvement, Error analysis

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Proceedings Article | 14 April 2014 Paper

Run time scanner data analysis for HVM lithography process monitoring and stability control

Woong Jae Chung, Young Ki Kim, John Tristan, Jeong Soo Kim, Lokesh Subramany, Chen Li, Brent Riggs, Vidya Ramanathan, Ram Karur-Shanmugam, George Hoo, Jie Gao, Anna Golotsvan, Kevin Huang, Bill Pierson, John Robinson

Proceedings Volume 9050, 90502J (2014) https://doi.org/10.1117/12.2046330

KEYWORDS: Optical alignment, Scanners, Semiconducting wafers, Lithography, Visualization, Data analysis, Statistical analysis, Atomic force microscopy, Visual analytics, Data modeling

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Proceedings Article | 2 April 2014 Paper

In-line focus monitoring and fast determination of best focus using scatterometry

Steven Thanh Ha, Benjamin Eynon, Melany Wynia, Jeff Schmidt, Christian Sparka, Antonio Mani, Roie Volkovich, SeungHoon Yoon, David Tien, John Robinson, Saroja Ramamurthi

Proceedings Volume 9050, 90502Y (2014) https://doi.org/10.1117/12.2047576

KEYWORDS: Semiconducting wafers, Scanners, Scatterometry, Optical design, Scatter measurement, Finite element methods, Metrology, Semiconductors, Matrices, Lithography

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Proceedings Article | 2 April 2014 Paper

Integrated production overlay field-by-field control for leading edge technology nodes

Woong Jae Chung, John Tristan, Karsten Gutjahr, Lokesh Subramany, Chen Li, Yulei Sun, Mark Yelverton, Young Ki Kim, Jeong Soo Kim, Chin-Chou Kevin Huang, William Pierson, Ramkumar Karur-Shanmugam, Brent Riggs, Sven Jug, John Robinson, Lipkong Yap, Vidya Ramanathan

Proceedings Volume 9050, 90501P (2014) https://doi.org/10.1117/12.2046076

KEYWORDS: Scanners, Semiconducting wafers, Overlay metrology, Control systems, Statistical modeling, Error analysis, Data modeling, Optical lithography, Process control, Atomic force microscopy

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Proceedings Article | 18 April 2013 Paper

Study of overlay in EUV/ArF mix and match lithography

Chin-Chou Kevin Huang, Lin Chua, KyungBae Hwang, Antonio Mani, Gino Marcuccilli, Bill Pierson, Ramkumar Karur-Shanmugam, John Robinson, Dongsub Choi, Michael Ferber, Klaus-Dieter Roeth, ByoungHoon Lee, Inhwan Lee

Proceedings Volume 8681, 86811O (2013) https://doi.org/10.1117/12.2011510

KEYWORDS: Semiconducting wafers, Extreme ultraviolet lithography, Photomasks, Overlay metrology, Personal protective equipment, Extreme ultraviolet, Scanners, Lithography, Control systems, Metrology

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Proceedings Article | 5 April 2012 Paper

Weighted least squares regression for advanced overlay control

Dana Klein, John Robinson, Guy Cohen, Chin-Chou Kevin Huang, Bill Pierson

Proceedings Volume 8324, 832425 (2012) https://doi.org/10.1117/12.916396

KEYWORDS: Overlay metrology, Data modeling, Metrology, Process control, Manufacturing, Semiconducting wafers, Optical filters, Control systems, Lithography, Integrated circuits

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Proceedings Article | 5 April 2012 Paper

Overlay control methodology comparison: field-by-field and high-order methods

Chun-Yen Huang, Chui-Fu Chiu, Wen-Bin Wu, Chiang-Lin Shih, Chin-Chou Kevin Huang, Healthy Huang, DongSub Choi, Bill Pierson, John Robinson

Proceedings Volume 8324, 832427 (2012) https://doi.org/10.1117/12.916427

KEYWORDS: Semiconducting wafers, Overlay metrology, Process control, Scanners, Lithography, Control systems, Metrology, Data modeling, Composites, Standards development

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Proceedings Article | 5 April 2012 Paper

Data feed-forward for improved optical CD and film metrology

L. Mihardja, M. Di, Q. Zhao, Z. Tan, J. Robinson, H. Chouaib

Proceedings Volume 8324, 83241H (2012) https://doi.org/10.1117/12.916405

KEYWORDS: Metrology, Critical dimension metrology, Optical metrology, Semiconducting wafers, Optics manufacturing, Time metrology, Dielectrics, 3D modeling, Process control, High volume manufacturing

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Proceedings Article | 20 April 2011 Paper

Improved overlay control using robust outlier removal methods

John Robinson, Osamu Fujita, Hiroyuki Kurita, Pavel Izikson, Dana Klein, Inna Tarshish-Shapir

Proceedings Volume 7971, 79711G (2011) https://doi.org/10.1117/12.879494

KEYWORDS: Overlay metrology, Data modeling, Metrology, Semiconductor manufacturing, Semiconductors, Semiconducting wafers, Process control, Numerical simulations, Data processing, Instrument modeling

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Proceedings Article | 20 April 2011 Paper

High-order stitching overlay analysis for advanced process control

Y. Pai, Charlie Chen, Louis Jang, Howard Chen, Chun-Chi Yu, Chin-Chou Huang, Hsing-Chien Wu, John Robinson, David Tien

Proceedings Volume 7971, 797127 (2011) https://doi.org/10.1117/12.879360

KEYWORDS: Overlay metrology, Data modeling, Semiconducting wafers, Process control, Metrology, Scanners, Optical lithography, Statistical modeling, Statistical analysis, Distortion

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Proceedings Article | 29 March 2011 Paper

Mask registration impact on intrafield on-wafer overlay performance

Guo-Tsai Huang, Alex Chen, Tung-Yaw Kang, S. C. Lee, Frank Laske, Klaus-Dieter Roethe, DongSub Choi, Chiang Reinhart, John Robinson, You Seung Jin, Lin Chua, David Tien, Venkat Nagaswami

Proceedings Volume 7971, 797106 (2011) https://doi.org/10.1117/12.879485

KEYWORDS: Photomasks, Semiconducting wafers, Overlay metrology, Scanners, Image registration, Error analysis, Optical lithography, Lithography, Double patterning technology, Reticles

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Proceedings Article | 2 April 2010 Paper

Automated optimized overlay sampling for high-order processing in double patterning lithography

Chiew-seng Koay, Matthew Colburn, Pavel Izikson, John Robinson, Cindy Kato, Hiroyuki Kurita, Venkat Nagaswami

Proceedings Volume 7638, 76381R (2010) https://doi.org/10.1117/12.846371

KEYWORDS: Semiconducting wafers, Statistical modeling, Lithography, Overlay metrology, Double patterning technology, Photomasks, Optical lithography, Metrology, Data modeling, Mathematical modeling

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Proceedings Article | 2 April 2010 Paper

Mask registration and wafer overlay

Chulseung Lee, Changjin Bang, Myoungsoo Kim, Hyosang Kang, Dohwa Lee, Woonjae Jeong, Ok-Sung Lim, Seunghoon Yoon, Jaekang Jung, Frank Laske, Lidia Parisoli, Klaus-Dieter Roeth, John Robinson, Sven Jug, Pavel Izikson, Berta Dinu, Amir Widmann, DongSub Choi

Proceedings Volume 7638, 76382I (2010) https://doi.org/10.1117/12.846321

KEYWORDS: Photomasks, Semiconducting wafers, Overlay metrology, Scanners, Pellicles, Metrology, Image registration, Distance measurement, Distortion, Double patterning technology

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Proceedings Article | 2 April 2010 Paper

Improved scanner matching using scanner fleet matcher (SFM)

Shian-Huan Cooper Chiu, Chin-Lung Lee, Sheng-Hsiung Yu, Kai-Lin Fu, Min-Hin Tung, Po-Chih Chen, Chao-Tien Huang, Chien-Chun Elsie Yu, Chin-Chou Huang, John Robinson, David Tien

Proceedings Volume 7638, 76382A (2010) https://doi.org/10.1117/12.846667

KEYWORDS: Scanners, Atomic force microscopy, Semiconducting wafers, Distortion, Overlay metrology, Software development, Metrology, Phase modulation, Performance modeling, Electronics

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Proceedings Article | 10 March 2010 Paper

Simultaneous optimization of dose and focus controls in advanced ArF immersion scanners

Tsuyoshi Toki, Pavel Izikson, Junichi Kosugi, Naruo Sakasai, Keiko Saotome, Kazuaki Suzuki, Daniel Kandel, John Robinson, Yuji Koyanagi

Proceedings Volume 7640, 764016 (2010) https://doi.org/10.1117/12.846413

KEYWORDS: Semiconducting wafers, Control systems, Finite element methods, Critical dimension metrology, Error analysis, Scanners, Neural networks, Scatter measurement, Scatterometry, Data modeling

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Proceedings Article | 24 March 2009 Paper

The study and simulation of high-order overlay control including field-by-field methodologies

Dongsub Choi, Chulseung Lee, Changjin Bang, Myoungsoo Kim, Hyosang Kang, James Manka, Seunghoon Yoon, Dohwa Lee, John Robinson

Proceedings Volume 7272, 727230 (2009) https://doi.org/10.1117/12.812935

KEYWORDS: Scanners, Semiconducting wafers, Overlay metrology, Data modeling, Semiconductors, Optical lithography, Optical alignment, Lithium, Control systems, Semiconductor manufacturing

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Proceedings Article | 24 March 2009 Paper

Improve scanner matching using automated real-time feedback control via scanner match maker (SMM)

Shian-Huan (Cooper) Chiu, Sheng-Hsiung Yu, Min-Hin Tung, Lei-Ken Wu, Ya-Tsz Yeh, James Manka, Chao-Tien (Healthy) Huang, John Robinson, Chin-Chou (Kevin) Huang, David Tien, YuYu Chen, Katsushi Makino, Jium-Ming Lin

Proceedings Volume 7272, 72723E (2009) https://doi.org/10.1117/12.814186

KEYWORDS: Scanners, Distortion, Semiconducting wafers, Overlay metrology, Phase modulation, Feedback control, Process control, Optical lithography, Metrology, Inspection

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Proceedings Article | 24 March 2009 Paper

Advanced modeling strategies to improve overlay control for 32-nm lithography processes

Anna Minvielle, Lovejeet Singh, Jeffrey Schefske, Joerg Reiss, Eric Kent, Terry Manchester, Brad Eichelberger, Kelly O'Brien, Jim Manka, John Robinson, David Tien

Proceedings Volume 7272, 72722X (2009) https://doi.org/10.1117/12.814256

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Scanners, Radium, Lithography, Visualization, Performance modeling, Immersion lithography, Double patterning technology

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Proceedings Article | 23 March 2009 Paper

Sampling for advanced overlay process control

Cindy Kato, Hiroyuki Kurita, Pavel Izikson, John Robinson

Proceedings Volume 7272, 727206 (2009) https://doi.org/10.1117/12.813568

KEYWORDS: Semiconducting wafers, Overlay metrology, Process control, Time metrology, Monte Carlo methods, Optical lithography, Statistical methods, Control systems, Immersion lithography, Lithography

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Proceedings Article | 16 April 2008 Paper

Sampling for advanced overlay process control

DongSub Choi, Pavel Izikson, Doug Sutherland, Kara Sherman, Jim Manka, John Robinson

Proceedings Volume 6922, 69222U (2008) https://doi.org/10.1117/12.772738

KEYWORDS: Overlay metrology, Semiconducting wafers, Process control, Metrology, Time metrology, Scanners, Error analysis, Optical lithography, Lithography, Fourier transforms

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Proceedings Article | 26 March 2008 Paper

A system to optimize mix-and-match overlay in lithography

Shinji Wakamoto, Yuuki Ishii, Koji Yasukawa, Shinroku Maejima, Atsuhiko Kato, John Robinson, Dong-Sub Choi

Proceedings Volume 6922, 69222V (2008) https://doi.org/10.1117/12.771778

KEYWORDS: Scanners, Distortion, Semiconducting wafers, Databases, Reticles, Lithography, Phase modulation, Overlay metrology, Distributed interactive simulations, Factor analysis

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Proceedings Article | 25 March 2008 Paper

In-line focus-dose monitoring for hyper NA imaging

Sara Loi, Alejandro Fasciszewski Zeballos, Umberto Iessi, John Robinson, Pavel Izikson, Antonio Mani, Marco Polli

Proceedings Volume 6922, 69223H (2008) https://doi.org/10.1117/12.772904

KEYWORDS: Semiconducting wafers, Metrology, Data modeling, Neural networks, Scanners, Lithography, 3D modeling, Diffractive optical elements, Finite element methods, Photoresist processing

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Proceedings Article | 5 April 2007 Paper

Litho cell control using MPX

Eric Apelgren, Harold Kennemer, Chris Nelson, Brad Eichelberger, John Robinson

Proceedings Volume 6518, 65182R (2007) https://doi.org/10.1117/12.712694

KEYWORDS: Semiconducting wafers, Scanners, Finite element methods, Metrology, Image processing, Calibration, Reticles, Data modeling, Wafer testing, Wafer-level optics

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Proceedings Article | 5 April 2007 Paper

Improved overlay control through automated high order compensation

S. Wakamoto, Y. Ishii, K. Yasukawa, A. Sukegawa, S. Maejima, A. Kato, J. Robinson, B. Eichelberger, P. Izikson, M. Adel

Proceedings Volume 6518, 65180J (2007) https://doi.org/10.1117/12.712710

KEYWORDS: Scanners, Distortion, Databases, Semiconducting wafers, Overlay metrology, Reticles, Control systems, Optical alignment, Lithography, Error analysis

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Proceedings Article | 24 March 2006 Paper

An integrated approach to the determination of a manufacturable process window in advanced microlithography

Marcelo Cusacovich, John Robinson, Shaunee Cheng, Greet Storms, Philippe Leray, Gian Lorusso

Proceedings Volume 6152, 615231 (2006) https://doi.org/10.1117/12.656503

KEYWORDS: Metrology, Scanning electron microscopy, Semiconducting wafers, Manufacturing, Finite element methods, Lithography, Resolution enhancement technologies, Design for manufacturing, Electroluminescence, Process control

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Proceedings Article | 10 May 2005 Paper

Utilizing overlay target noise metrics for improved process control

Sean Hannon, John Robinson, Marcelo Cusacovich, Chris Nelson, Harold Kennemer

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.600153

KEYWORDS: Overlay metrology, Metrology, Process control, Process modeling, Semiconducting wafers, Image processing, Diagnostics, Metals, Statistical analysis, Visibility

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Proceedings Article | 24 May 2004 Paper

A comparison of methods for in-chip overlay control at the 65-nm node

John Robinson, Mark Stakely, Jorge Poplawski, Pavel Izikson, Elyakim Kassel, Mike Adel

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534510

KEYWORDS: Overlay metrology, Metrology, Scanners, Error analysis, Reticles, Semiconducting wafers, Personal protective equipment, Lithography, Data modeling, Data acquisition

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Proceedings Article | 24 May 2004 Paper

Scanner overlay mix and match matrix generation: capturing all sources of variation

Stephen DeMoor, Jay Brown, John Robinson, Simon Chang, Colin Tan

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534359

KEYWORDS: Scanners, Semiconducting wafers, Data modeling, Optical alignment, Overlay metrology, Error analysis, Matrices, Statistical modeling, Phase modulation, Metrology

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Proceedings Article | 29 April 2004 Paper

Yield loss in lithographic patterning at the 65nm node and beyond

Kevin Monahan, Brad Eichelberger, Matt Hankinson, John Robinson, Mike Slessor

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.537349

KEYWORDS: Critical dimension metrology, Lithography, Semiconducting wafers, Process control, Spectroscopic ellipsometry, Metrology, Manufacturing, Overlay metrology, Photomasks, Resolution enhancement technologies

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Proceedings Article | 2 June 2003 Paper

Performance study of new segmented overlay marks for advanced wafer processing

Mike Adel, John Allgair, David Benoit, Mark Ghinovker, Elyakim Kassel, C. Nelson, John Robinson, Gary Seligman

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483477

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Optical design, Data modeling, Lithography, Metals, Image segmentation, Optical lithography, Imaging metrology

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Proceedings Article | 2 June 2003 Paper

Lithography and metrology overlay troubleshooting by advanced query and multivariate analysis

Bernd Schulz, Jens Krause, John Robinson, Craig MacNaughton

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483470

KEYWORDS: Overlay metrology, Semiconducting wafers, Data modeling, Databases, Lithography, Metrology, Statistical analysis, Data analysis, Metals, Back end of line

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Proceedings Article | 22 August 2001 Paper

Characterization of optical proximity correction features

John Allgair, Michelle Ivy, Kevin Lucas, John Sturtevant, Richard Elliott, Chris Mack, Craig MacNaughton, John Miller, Mike Pochkowski, Moshe Preil, John Robinson, Frank Santos

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436743

KEYWORDS: Optical proximity correction, Reticles, Photomasks, Lithography, Scanning electron microscopy, Critical dimension metrology, Etching, Semiconducting wafers, Tolerancing, Optical lithography

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Proceedings Article | 2 June 2000 Paper

Manufacturing considerations for implementation of scatterometry for process monitoring

John Allgair, David Benoit, Robert Hershey, Lloyd Litt, Ibrahim Abdulhalim, William Braymer, Michael Faeyrman, John Robinson, Umar Whitney, Yiping Xu, Piotr Zalicki, Joel Seligson

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386465

KEYWORDS: Scatterometry, Reflectivity, Scanning electron microscopy, Critical dimension metrology, Metrology, Silicon, Atomic force microscopy, Manufacturing, Process control, Semiconducting wafers

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Proceedings Article | 14 June 1999 Paper

Characterization of overlay tolerance requirements for via to metal alignment

John Allgair, Mike Schippers, Brad Smith, Richard Elliott, John Miller, John Robinson

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350811

KEYWORDS: Oxides, Overlay metrology, Scanning electron microscopy, Critical dimension metrology, Tolerancing, Copper, Metals, Electrical breakdown, Optical alignment, Resistance

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Showing 5 of 49 publications

Proceedings Volume Editor (4)

SPIE Conference Volume | 24 May 2023

Metrology, Inspection, and Process Control XXXVII

SPIE Conference Volume | 5 July 2022

Metrology, Inspection, and Process Control XXXVI

SPIE Conference Volume | 15 April 2021

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

SPIE Conference Volume | 10 April 2020

Metrology, Inspection, and Process Control for Microlithography XXXIV

Conference Committee Involvement (16)

Metrology, Inspection, and Process Control XXXIX

23 February 2025 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVIII

26 February 2024 | San Jose, California, United States

SPIE Advanced Lithography + Patterning

25 February 2024 | San Jose, United States

Metrology, Inspection, and Process Control XXXVII

27 February 2023 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVI

25 April 2022 | San Jose, California, United States

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

22 February 2021 | Online Only, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXIV

24 February 2020 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXIII

25 February 2019 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXII

26 February 2018 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXI

27 February 2017 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXX

22 February 2016 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXIX

23 February 2015 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVIII

24 February 2014 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVII

25 February 2013 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVI

13 February 2012 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXV

28 February 2011 | San Jose, California, United States

Showing 5 of 16 Conference Committees

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