As the semiconductor industry rapidly approaches lithography nodes beyond 3nm, On Product Overlay (OPO) becomes a critical factor in enabling process control and manufacturing yield. The correspondingly tight OPO error budget emphasizes the importance of accurate overlay (OVL) metrology for capturing and tracking ever-smaller processes and patterning variations. In the DRAM memory segment, additional challenges arise in layers around the storage node, where the critical patterning steps are on thick layers with denser patterns than on other layers. A major challenge for optical overlay measurement on storage node layers comes from opaque optical stack materials whose optical properties reduce signal penetration effectiveness. Another key challenge is the high aspect ratio between the stack height and the target pitch, reducing diffraction efficiency and sensitivity. IBO (Image-Based Overlay) studies have shown that long wavelength (WL) improves the measurability of thick layers and significantly improves overlay results. In this paper, it is reported that longer WL (>800nm) can overcome the measurability challenges and achieve accurate results on a DRAM storage node layer. We present how improvements in raw overlay signal (pupil-plane image uniformity) further result in Total Measurement Uncertainty (TMU) and residual improvements over previous baseline solutions. Long WL enables DRAM manufacturers to meet and tighten OPO specifications on thick, storage node layers in their advanced technology architectures.
As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
In this paper, the rAIMTM (robust AIM) overlay target was investigated in terms of the stability versus the POR AIM® (Advanced Imaging Metrology) target used for imaging-based overlay (IBO) measurement at after development inspection (ADI). The targets were designed using KLA’s MTD AcuRate™, metrology target design software that performs simulations based on the optical properties related to relative permittivity and permeability about the material of each of the layers. Using advanced device layers, we studied the performance of the POR AIM target versus the newly designed rAIM target for imaging-based overlay measurements. For each target, we quantified the optical contrast, kernel signal, correctable modeled terms, total measurement uncertainty (TMU), and overlay (OVL) residuals from the modeled data through various wavelengths inside the Moiré effect regime in the case of rAIM. We demonstrate that there is an OVL measurement performance improvement using the rAIM target versus the POR AIM target. The measured optical properties of the rAIM target and comparison to the POR AIM target will be presented.
Critical dimension uniformity (CDU) control using dose correction is well established and has relied on traditional polynomial models like Zernike and Legendre for a long time. As process margins are shrinking and CD (and CDU) control becomes a significant contributor to edge placement error (EPE), the dose correction models need to be enhanced to represent the systematic behavior of the fingerprints more precisely. In this paper we show that many CD signatures over the exposure field or over the wafer cannot be corrected efficiently using classical polynomials. As the CD signatures can come from a variety of processes like etch, CVD, polish, or deposition, a flexible model approach is required. Furthermore, making the right decision when choosing the correct model order of the classical polynomial based model is complicated as we need to handle the balance between the degrees of freedom and minimizing the residuals. With this problem statement in mind, we introduce a novel radial basis function (RBF) modeling approach for dose corrections that can correct a wide range of signatures. The new modeling approach is verified on real CD signatures on product, reducing CDU significantly. Additionally, we demonstrate that this approach can make the life of the engineers easy again, as there are no prior decisions about model type and order needed.
Overlay metrology plays a significant role in process and yield control for integrated circuit (IC) manufacturing. As the On-Product Overlay (OPO) in advance nodes is reduced to a few nanometers, a very small margin is left for measurement inaccuracy. We introduce a multi-wavelength (spectral) analysis and measurement method, capable of characterizing overlay inaccuracy signatures on the wafer, and quantifying and removing the inaccuracy portion of the overlay measurement, resulting in a more accurate measurement, better process control, and yield enhancement. This method was applied to SK hynix’s advanced process production wafers, demonstrating an enhancement in accuracy over single-wavelength based overlay measurements.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
Reduction in on product overlay (OPO) is a key component for high-end, high yield integrated circuit manufacturing. Due to the continually shrinking dimensions of the IC device elements it has become near-impossible to measure overlay on the device itself, driving the need to perform overlay measurements on dedicated overlay targets. In order to enable accurate measurement on grid (target) in terms of OPO matching, the overlay mark must be as similar as possible to the device in order to mimic the process impact on the device. Imaging-based optical overlay (IBO) provides the best accuracy and robustness for overlay metrology measurements for many process layers. To further optimize IBO performance, a new robust AIM (rAIM™) IBO target design was developed, using the Moiré effect. rAIM is implemented using significantly smaller pitches compared with the standard AIM® target, hence providing a more device-like target design. This new target design has the potential to improve target accuracy and robustness, to improve measurability, and to meet overlay basic performance requirements, such as total measurement uncertainty (TMU).
We developed a statistical method that can be applied to overlay metrology tools to improve performance and time-to-results (TTR) of multi-cycle optimization based on the brute force method. First, we evaluated full response surfaces for each combination of the discrete equipment settings and calculated desirability scores using a normalization function. Second, we combined gradient optimization techniques and response surface methodologies to find the important local maxima (center of the islands in quadratic contour) and stationary response points. Once all the stationary response points have been identified, users can choose to rank the solutions by quality or can choose to use analysis of variance (ANOVA) methods to determine which main effects and/or interactions are of interest. Two separate layers were evaluated and compared to the process of reference (POR) brute force method of optimization. Results showed that the best residuals values from recipes optimized using 1-cycle SPOC-based automatic recipe optimization (ARO) and ARO based on the 2- cycle Brute-Force strategy were comparable to known residuals values from the POR recipes. Moreover, SPOC-based ARO was performed with a TTR of under 2 hours, while a 2-cycle Brute-Force ARO typically took 6~ 20 hours depending on specific configurations. The vast reduction in optimization time is primarily attributed to the elimination of multi-cycle refinement, whose data collection dominated the previously observed TTR. In conclusion, we demonstrated the ability to reduce time to solution by a factor of 3 while maintaining or improving on overlay residuals compared to existing brute force methodologies.
As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancements are required to meet these demands. Color Per Layer (CPL) is a unique imaging overlay metrology approach that enables the measurement of each layer with individually-optimized wavelength and focus position. CPL allows the user to custom-define the most suitable conditions per layer, thereby ensuring optimal performance. Imaging-based overlay (IBO) utilizes CPL in order to overcome inaccuracies due to interactions between bottom and top layers. These layers are fundamentally different in that the top grating is usually the photoresist layer, but the bottom grating can be any process layer. Therefore, optimizing the conditions for each layer will maximize measurement accuracy. KLA’s Archer™ 700 metrology tool addresses these metrology challenges by putting CPL to use, where the Wave Tuner (WT) allows the user to select a specific wavelength. This paper presents this novel CPL approach and discusses its reduction in OPO and contrast, and reviews use cases from DRAM and 3D NAND. We will present the results from these case studies, focusing on SK Hynix DRAM production wafers.
Overlay process control is a critical aspect of integrated circuit manufacturing. Advanced DRAM manufacturing overlay error budget approaches the sub-2nm threshold, including all sources of overlay error: litho processing, non-litho processing, metrology error, etc. Overlay measurement quality, both for accuracy and robustness, depends on the metrology system and its recipe setup. The optimal configuration depends on the layer and materials involved. Increased flexibility of metrology setup is of paramount importance, paired with improved methods of recipe optimization.
Both optical image-based overlay (IBO) and scatterometry diffraction overlay (SCOL®) are necessary tools for overlay control. For some devices and layers IBO provides the best accuracy and robustness, while on others SCOL provides optimum metrology. Historically, wavelength selection was limited to discrete wavelengths and at only a single wavelength. At advanced nodes IBO and SCOL require wavelength tunability and multiple wavelengths to optimize accuracy and robustness, as well as options for polarization and numerical aperture (NA). In previous studies1,2,3 we investigated wavelength tunability analysis with landscape analysis, using analytic techniques to determine the optimal setup. In this report we show advancements in the landscape analysis technique for IBO through both focus and wavelength, and comparisons to SCOL. A key advantage of imaging is the ability to optimize wavelength on a per-layer basis. This can be a benefit for EUV layers in combination with those of 193i, for example, as well as other applications such as thick 3D NAND layers. The goal is to make accurate and robust overlay metrology that is immune from process stack variations, and to provide metrics that indicate the quality of metrology performance. Through both simulation and on-wafer advanced DRAM measurements, we show quantitative benefits of accuracy and robustness to process stack variability for IBO and SCOL applications.
Methodologies described in this work can be achieved using Archer™ overlay metrology systems, ATL™ overlay metrology systems, and 5D Analyzer® advanced data analysis and patterning control solution.
In the leading-edge production measuring the geometrical dimensions with e-beam inspection (CD-SEM data) or scatterometry technology (OCD data) is one of the most time-consuming steps without adding value to the wafer. Hence the fabs want to limit the effort to minimize the costs per wafer. On the other hand, the output of the metrology steps is needed to feed the SPC and APC systems with sufficient information. We handle that trade-off with a new sampling scheme optimizer supporting CD-SEM and OCD data.
Generally, we can use the sampling scheme optimization for a set of different features and their measured parameters in parallel. Especially in logic, but also for memory, the focus and dose dependencies of several features may be different. Hence, we optimized the distribution of the measured sites to create a perfect representation of the systematic fingerprint for all important anchor features within one single sampling scheme.
For the verification of the approach we investigated two cases. The first case are dense CD measurements, which are usually needed to create and update intra-field dose corrections. We minimize the number of measured sites significantly and distribute the remaining sites over different fields to ensure a good coverage of the systematic effects. Finally, that allows us a much higher update frequency of the dose corrections and yields in smaller CDU values.
The second case optimized the throughput of an OCD metrology system. The applied high-density sampling scheme for the focus monitoring done on reference wafers takes a lot of time during measuring. That specific type of measurement is done for monitoring and updating the focus reference corrections. With our proposed solution, we can achieve the same quality with respect to the reference measurement with more 50% less measured sites.
In next generation 3D-NAND devices, accurately determining after-etch overlay for the multi-layer stack is a major challenge. This is especially the case for the multi-tier 3D-NAND structures, where the overlay of the channel holes is an important performance parameter. The most commonly used after-etch metrology suffer both from the high aspect ratio of the channel holes and from the potential presence of large tilts.
Using In-Device Metrology (IDM), we show results of non-destructive overlay measurements on 3D-NAND memory holes. Once the overlay signal has been determined, the remaining asymmetry information in the measurement can be used to characterize tilt phenomena densely through the memory array.
Using hyper-dense in-device measurements show the overlay effects of intra-die stress. A new lithography scanner model is used to correct specifically for such intra-die overlay fingerprints.
In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups are suitable for the metrology method as different setups can yield significantly different performance in terms of the accuracy and robustness of the reported OVL values. Finding an optimal measurement setup requires great flexibility in measurement, to allow for high-resolution landscape mapping (mapping the dependence of OVL, other metrics, and details of pupil images on measurement setup). This can then be followed by a method for analyzing the landscape and selecting an accurate and robust measurement setup. The selection of an optimal measurement setup is complicated by the sensitivity of metrology to variations in the fabrication process (process variations) such as variations in layer thickness or in the properties of target symmetry. The metrology landscape changes with process variations and maintaining optimal performance might require continuous adjustments of the measurement setup. Here we present a method for the selection and adjustment of an optimal measurement setup. First, the landscape is measured and analyzed to calculate theory-based accurate OVL values as well as quality metrics which depend on details of the pupil image. These OVL values and metrics are then used as an internal ruler (“self-reference”), effectively eliminating the need for an external reference such as CD-SEM. Finally, an optimal measurement setup is selected by choosing a setup which yields the same OVL values as the self-reference and is also robust to small changes in the landscape. We present measurements which show how a SCOL landscape changes within wafer, wafer to wafer, and lot to lot with intentionally designed process variations between. In this case the process variations cause large shifts in the SCOL landscape and it is not possible to find a common optimal measurement setup for all wafers. To deal with such process variations we adjust the measurement setup as needed. Initially an optimal setup is chosen based on the first wafer. For subsequent wafers the process stability is continuously monitored. Once large process variations are detected the landscape information is used for selecting a new measurement setup, thereby maintaining optimal accuracy and robustness. Methods described in this work are enabled by the ATL (Accurate Tunable Laser) scatterometry-based overlay metrology system.
KEYWORDS: Semiconducting wafers, Metrology, Critical dimension metrology, Scanners, Process control, Modulation, Scatterometry, Finite element methods, Signal to noise ratio, Single crystal X-ray diffraction
Lithography process control solutions require more exacting capabilities as the semiconductor industry goes forward to the 1x nm node DRAM device manufacturing. In order to continue scaling down the device feature sizes, critical dimension (CD) uniformity requires continuous improvement to meet the required CD error budget. In this study we investigate using optical measurement technology to improve over CD-SEM methods in focus, dose, and CD. One of the key challenges is measuring scanner focus of device patterns. There are focus measurement methods based on specially designed marks on scribe-line, however, one issue of this approach is that it will report focus of scribe line which is potentially different from that of the real device pattern. In addition, scribe-line marks require additional design and troubleshooting steps that add complexity. In this study, we investigated focus measurement directly on the device pattern. Dose control is typically based on using the linear correlation behavior between dose and CD. The noise of CD measurement, based on CD-SEM for example, will not only impact the accuracy, but also will make it difficult to monitor dose signature on product wafers. In this study we will report the direct dose metrology result using an optical metrology system which especially enhances the DUV spectral coverage to improve the signal to noise ratio. CD-SEM is often used to measure CD after the lithography step. This measurement approach has the advantage of easy recipe setup as well as the flexibility to measure critical feature dimensions, however, we observe that CD-SEM metrology has limitations. In this study, we demonstrate within-field CD uniformity improvement through the extraction of clean scanner slit and scan CD behavior by using optical metrology.
As semiconductor manufacturing technology progresses and the dimensions of integrated circuit elements shrink, overlay budget is accordingly being reduced. Overlay budget closely approaches the scale of measurement inaccuracies due to both optical imperfections of the measurement system and the interaction of light with geometrical asymmetries of the measured targets. Measurement inaccuracies can no longer be ignored due to their significant effect on the resulting device yield. In this paper we investigate a new approach for imaging based overlay (IBO) measurements by optimizing accuracy rather than contrast precision, including its effect over the total target performance, using wavelength tunable overlay imaging metrology. We present new accuracy metrics based on theoretical development and present their quality in identifying the measurement accuracy when compared to CD-SEM overlay measurements. The paper presents the theoretical considerations and simulation work, as well as measurement data, for which tunability combined with the new accuracy metrics is shown to improve accuracy performance.
Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after litho control loop typically involves high frequency sampling: every lot or nearly every lot. An after etch overlay metrology step is often included, at a lower sampling frequency, in order to characterize and compensate for bias. The after etch metrology step often involves CD-SEM metrology, in this case in-cell and ondevice. This work explores an alternative approach using spectroscopic ellipsometry (SE) metrology and a machine learning analysis technique. Advanced 1x nm DRAM wafers were prepared, including both nominal (POR) wafers with mean overlay offsets, as well as DOE wafers with intentional across wafer overlay modulation. After litho metrology was measured using optical imaging metrology, as well as after etch metrology using both SE and CD-SEM for comparison. We investigate 2 types of machine learning techniques with SE data: model-less and model-based, showing excellent performance for after etch in-cell on-device overlay metrology.
Overlay control based on DI metrology of optical targets has been the primary basis for run-to-run process control for many years. In previous work we described a scenario where optical overlay metrology is performed on metrology targets on a high frequency basis including every lot (or most lots) at DI. SEM based FI metrology is performed ondevice in-die as-etched on an infrequent basis. Hybrid control schemes of this type have been in use for many process nodes. What is new is the relative size of the NZO as compared to the overlay spec, and the need to find more comprehensive solutions to characterize and control the size and variability of NZO at the 1x nm node: sampling, modeling, temporal frequency and control aspects, as well as trade-offs between SEM throughput and accuracy.
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