Directed Self Assembly (DSA) has gained increased momentum in recent years as a cost-effective means for extending lithography to sub-30nm pitch, primarily presenting itself as an alternative to mainstream 193i pitch division approaches such as SADP and SAQP. Towards these goals, IMEC has excelled at understanding and implementing directed self-assembly based on PS-b-PMMA block co-polymers (BCPs) using LiNe flow [1]. These efforts increase the understanding of how block copolymers might be implemented as part of HVM compatible DSA integration schemes. In recent contributions, we have proposed and successfully demonstrated two state-of-the-art CMOS process flows which employed DSA based on the PS-b-PMMA, LiNe flow at IMEC (pitch = 28 nm) to form FinFET arrays via both a ‘cut-last’ and ‘cut-first’ approach [2-4]. Therein, we described the relevant film stacks (hard mask and STI stacks) to achieve robust patterning and pattern transfer into IMEC’s FEOL device film stacks. We also described some of the pattern placement and overlay challenges associated with these two strategies. In this contribution, we will present materials and processes for FinFET patterning and integration towards sub-20 nm pitch technology nodes. This presents a noteworthy challenge for DSA using BCPs as the ultimate resolution for PS-b-PMMA may not achieve such dimensions. The emphasis will continue to be towards patterning approaches, wafer alignment strategies, the effects of DSA processing on wafer alignment and overlay.
KEYWORDS: Metrology, Algorithm development, Software development, Data modeling, Image processing, Semiconductors, Scanning electron microscopy, Image analysis, Data analysis, Process control
The dimensional scaling in IC manufacturing strongly drives the demands on CD and defect metrology techniques and their measurement uncertainties. Defect review has become as important as CD metrology and both of them create a new metrology paradigm because it creates a completely new need for flexible, robust and scalable metrology software. Current, software architectures and metrology algorithms are performant but it must be pushed to another higher level in order to follow roadmap speed and requirements. For example: manage defect and CD in one step algorithm, customize algorithms and outputs features for each R&D team environment, provide software update every day or every week for R&D teams in order to explore easily various development strategies. The final goal is to avoid spending hours and days to manually tune algorithm to analyze metrology data and to allow R&D teams to stay focus on their expertise. The benefits are drastic costs reduction, more efficient R&D team and better process quality.
In this paper, we propose a new generation of software platform and development infrastructure which can integrate specific metrology business modules. For example, we will show the integration of a chemistry module dedicated to electronics materials like Direct Self Assembly features. We will show a new generation of image analysis algorithms which are able to manage at the same time defect rates, images classifications, CD and roughness measurements with high throughput performances in order to be compatible with HVM. In a second part, we will assess the reliability, the customization of algorithm and the software platform capabilities to follow new specific semiconductor metrology software requirements: flexibility, robustness, high throughput and scalability. Finally, we will demonstrate how such environment has allowed a drastic reduction of data analysis cycle time.
Directed self-assembly (DSA) of block copolymers (BCP) has attracted significant interest as a patterning technique over the past few years. We have previously reported the development of a new process flow, the CHIPS flow (Chemo-epitaxy Induced by Pillar Structures), where we use ArFi lithography and plasma etch to print guiding pillar patterns for the DSA of cylindrical phase BCPs into dense hexagonal hole arrays of 22.5 nm half-pitch and 15 nm half-pitch [1]. The ability of this DSA process to generate dense regular patterns makes it an excellent candidate for patterning memory devices. Thus, in this paper we study the applicability of the CHIPS flow to patterning for DRAM storage layers. We report the impact of various process conditions on defect density, defect types and pattern variability. We also perform detailed analysis of the DSA patterns, quantify pattern placement accuracy and demonstrate a route towards excellent LCDU after pattern transfer into a hard mask layer.
Pattern collapse currently limits the achievable resolution of the highest resolving EUV photoresists available. The causes of pattern collapse include the surface tension of the rinse liquid and the shrinkage of the resist pattern during the drying step. If these collapse mechanisms can be successfully mitigated with process approaches that do not require changes to the resist itself, the ultimate resolution of existing EUV resists can be improved. Described here is a dry development rinse process, applicable to existing EUV photoresists, which prevents pattern collapse to both improve ultimate resolution and the process window of currently resolvable features. Reducing the burden of collapse prevention on the resist also allows improvements in line width roughness (LWR) and cross section profile and provides additional degrees of freedom for future resist design.
Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for sub-10nm nodes and present itself as an alternative pitch division approach. As a result, DSA has gained increased momentum in recent years, as a means for extending optical lithography past its current limits. The availability of a DSA processing line can enable to further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography.
The patterning potential of block copolymer (BCP) materials via various directed self-assembly (DSA) schemes has been demonstrated for over a decade. We have previously reported the HONEYCOMB flow; a process flow where we utilize Extreme Ultraviolet Lithography and Oxygen plasma to guide the assembly of cylindrical phase BCPs into regular hexagonal arrays of contact holes [1, 2]. In this work we report the development of a new process flow, the CHIPS flow, where we use ArFi lithography to print guiding patterns for the chemo-epitaxial DSA of BCPs. Using this process flow we demonstrate BCP assembly into hexagonal arrays with sub-25 nm half-pitch and discuss critical steps of the process flow. Additionally, we discuss the influence of under-layer surface energy on the DSA process window and report contact hole metrology results.
Numerous block copolymer (BCP) systems can be used in directed self-assembly (DSA) processes to form patterns useful in lithography, especially lines and spaces with lamellar phase systems and vias/pillars with cylindrical phase systems. However, most of these BCP systems with attractive pattern formation capabilities have limited plasma etch contrast between the polymer domains. One potential solution to greatly enhance this etch contrast is a recently developed technique called sequential infiltration synthesis (SIS). SIS is a self-limiting synthesis technique, like atomic layer deposition, where organometallic (OM) precursor vapours and oxidants are introduced into self-assembled block copolymer systems in multiple cycles. In the first half of each cycle the OM precursor selectively reacts with one polymer domain, and in the second half of the cycle the oxidant reacts with the OM groups in the polymer film to selectively form metallic compounds in one of the polymer domains. Thus, the polymer pattern is transformed into a metallic mask with much enhanced plasma etch contrast. We report the effects of such a block-selective SIS process of metallic compounds on the feature sizes, roughness and profiles of patterns formed with BCP systems.
The patterning potential of block copolymer materials via various directed self-assembly (DSA) schemes has been demonstrated for over a decade. At cost-effective low printing doses, extreme ultra-violet lithography (EUVL) suffers from shot noise effects while patterning sub 30 nm contact hole dimensions. As the critical dimension (CD) of DSA systems is largely determined by polymer dimensions, it is theoretically expected that the local CD uniformity (LCDU) of EUVL pre-patterns can be improved by the DSA of pitch matched block co-polymers. In this work we demonstrate continued improvements on our previously reported chemo-epitaxy DSA integration flow. Also, we achieve dense arrays of contact holes via 3x and 4x frequency multiplication of EUVL patterned contact hole arrays.
One critical problem with EUV patterning is the local CD variation of contact holes. The issue is especially problematic for patterning of sub-30nm hole dimensions. Although the EUV wavelength enables resolution of fine contact patterns, shot noise effects (both chemical and optical) result in high levels of CD non-uniformity. Directed self-assembly (DSA) offers the possibility of rectifying this non-uniformity. Since the resulting CD in this patterning approach is typically dictated by the polymer size, application of this technology in conjunction with an EUV-defined pre-pattern can theoretically improve the local CD uniformity. Integration approaches using both chemo- and grapho-epitaxy integration may be used to achieve DSA enabled uniformity improvement. The drawbacks and benefits of both approaches will be discussed. Finally, these types of DSA flows also enable frequency multiplication to achieve dense arrays from an initially sparse pattern. In this study, we will report on a variety of schemes to attain rectification and frequency multiplication.
Printing technology is a low cost technique for the processing of organic electronic devices. Here, we report printing characteristics of poly (3,4-ethylenedioxythiophene) : poly (styrenesulfonate) (PEDOT:PSS), typically used as hole injection/transport layer in various organic devices e.g. organic light emitting diodes, solar cells, and field effect transistors. In this work, we optimize drop spacing and substrate temperature during ink-jet printing of PEDOT:PSS films on rigid (glass) and flexible (PET) substrates. Morphological characterization of the films was performed using optical and scanning electron microscopy. Optical transmittance was measured using UV-Vis spectrophotometer and sheet resistance of the films was measured using four-point probe technique. We find that substrate temperature and drop spacing significantly affect the morphology, in our case decreasing these lead to smooth morphology of the ink-jet printed PEDOT-PSS films.
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