As lithography patterning focus tolerance shrinkage in advanced production fab, defocus due to scanner wafer table or pre-layer contamination has been considered as a yield-loss killer and wafer scrap contributor. Traditionally, we can only apply a fixed by-wafer/by-zone spec to monitor leveling performance, lacking flexibility for further defense system design or root-cause analysis. In this paper we develop a comprehensive solution to capture focus/chuck spot in a high-volume manufacturing environment. This algorithm can automatically detect and categorize defocus spot into focus and chuck spots. Meanwhile, this algorithm produces an overlapped map for back-tracing pre-stage contamination and regularly send an alarm in customized schedule to prevent serious yield loss.
In a leading-edge high-volume manufacturing fab, lithographers focus on searching for a suitable alignment layout strategy to cover process-induced overlay variation. However, how to minimize scanner cross-chuck overlay impact also draws attention due to WPH loss from chuck dedication. In this paper we evaluate a novel algorithm to analyze lithography scanner process/metrology data and introduce a new KPI called “model accuracy” for alignment sampling layout strategy creation, which takes into account robustness index as wafer-to-wafer/chuck-to-chuck variation. Combined with simulated overlay performance, an optimal alignment layout strategy is recommended for a maximum coverage of cross-chuck overlay, which leads to maximum productivity.
In recent years, advances in semiconductor technologies have resulted in the continuous shrinkage of the process window required to fabricate a device, and specifically, the shrinkage of the overall overlay budget of the critical layers. Among other variables, a key contributor of wafer-to-wafer overlay variations is scanner alignment strategy. In high-volume manufacturing (HVM), the reduction in alignment mark count can lead to productivity improvement, however, that tradeoff impacts the scanner alignment layout and overlay model performance. In this paper, we present a comprehensive investigation of an in-line production experiment and simulation results to evaluate overlay performance by cooptimization of scanner alignment mark count, layout for High Order Wafer Alignment (HOWA) model.
Stitching process is a widely adopted technique in manufacturing of image sensors to overcome reticle size limitations. In order to accomplish successful stitching, both standard overlay target data and stitching data from stitching marks need to be monitored and controlled. Large overlay will result in faulty electric connections between layers, and therefore result in chip failure. Similarly, large stitching also could cause the poor contact between neighboring sub-chips, and consequently result in device malfunction. In this article, we propose three novel methods to enable the correction per exposure (CPE) model for stitching and overlay control. With the implementation of these methods, the stitching and overlay residual are significantly improved compared with current solutions.
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