Dr. Valery Axelrad Profile

Dr. Valery Axelrad

at Sequoia Design Systems Inc

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Author

Publications (23)

Proceedings Article | 9 July 2015 Paper

Pitch-based pattern splitting for 1D layout

Ryo Nakayama, Hiroyuki Ishii, Koji Mikami, Koichiro Tsujita, Hidetami Yaegashi, Kenichi Oyama, Michael Smayling, Valery Axelrad

Proceedings Volume 9658, 96580A (2015) https://doi.org/10.1117/12.2192529

KEYWORDS: Optical lithography, Photomasks, Source mask optimization, Lithography, Etching, Scanning electron microscopy, Logic devices, Computer programming, Photovoltaics, Metals

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Proceedings Article | 18 March 2015 Paper

7nm logic optical lithography with OPC-Lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Ryo Nakayama, Kenichi Oyama, Shohei Yamauchi, Hiroyuki Ishii, Koji Mikami

Proceedings Volume 9426, 94261U (2015) https://doi.org/10.1117/12.2084846

KEYWORDS: Optical lithography, Logic, Double patterning technology, Etching, Optical proximity correction, Photomasks, Source mask optimization, Neodymium, Fiber optic illuminators, Picosecond phenomena

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The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity and process margin.[1] As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary.

For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.[5]

In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments.

Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design.

Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]

Proceedings Article | 16 September 2014 Paper

OPC-Lite for gridded designs at low k1

V. Axelrad, M. Smayling, K. Tsujita, K. Mikami, H. Yaegashi

Proceedings Volume 9235, 92350C (2014) https://doi.org/10.1117/12.2069353

KEYWORDS: Optical proximity correction, Lithography, Double patterning technology, Critical dimension metrology, Manufacturing, Photomasks, Optics manufacturing, Scanning electron microscopy, Databases, Image processing

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Proceedings Article | 31 March 2014 Paper

Characterization of 1D layout technology at advanced nodes and low k1

V. Axelrad, K. Mikami, M. Smayling, K. Tsujita, H. Yaegashi

Proceedings Volume 9052, 905213 (2014) https://doi.org/10.1117/12.2046120

KEYWORDS: Field effect transistors, Optical lithography, Lithography, Manufacturing, Double patterning technology, Device simulation, Photomasks, Calibration, Image processing, Photovoltaics

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Proceedings Article | 31 March 2014 Paper

11nm logic lithography with OPC-lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Ryo Nakayama, Kenichi Oyama, Arisa Hara

Proceedings Volume 9052, 90520M (2014) https://doi.org/10.1117/12.2045667

KEYWORDS: Logic, Photomasks, Semiconducting wafers, Optical proximity correction, Source mask optimization, Fiber optic illuminators, Lithography, Double patterning technology, Etching, Convolution

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Proceedings Article | 12 April 2013 Paper

Sub-12nm optical lithography with 4x pitch division and SMO-lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Tadashi Arai, Kenichi Oyama, Arisa Hara

Proceedings Volume 8683, 868305 (2013) https://doi.org/10.1117/12.2011329

KEYWORDS: Optical lithography, Photomasks, Logic, Optical proximity correction, Double patterning technology, Semiconducting wafers, Transmission electron microscopy, Source mask optimization, Neodymium, Etching

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Proceedings Article | 8 November 2012 Paper

Improvement of lithographic performance and reduction of mask cost by simple OPC

Koichiro Tsujita, Koji Mikami, Hiroyuki Ishii, Tadashi Arai, Ryo Nakayama, Michael Smayling, Valery Axelrad, Hidetami Yaegashi, Kenichi Oyama

Proceedings Volume 8522, 852209 (2012) https://doi.org/10.1117/12.961118

KEYWORDS: Photomasks, Optical proximity correction, Source mask optimization, Metals, Lithography, Photovoltaics, Semiconducting wafers, Scanning electron microscopy, SRAF, Inspection

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Proceedings Article | 13 March 2012 Paper

Sub-20nm logic lithography optimization with simple OPC and multiple pitch division

Michael Smayling, Valery Axelrad, Koichiro Tsujita, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, Yuichi Gyoda

Proceedings Volume 8326, 832613 (2012) https://doi.org/10.1117/12.914916

KEYWORDS: Optical proximity correction, Logic, Photomasks, Optical lithography, Etching, Lithography, Acquisition tracking and pointing, Photovoltaics, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 23 March 2011 Paper

Optical lithography applied to 20-nm CMOS Logic and SRAM

V. Axelrad, M. Smayling, K. Tsujita, K. Takahashi

Proceedings Volume 7973, 797314 (2011) https://doi.org/10.1117/12.879522

KEYWORDS: Logic, Scanners, Source mask optimization, Optical lithography, Lithography, Transistors, 193nm lithography, Lithographic illumination, Cadmium, Double patterning technology

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Proceedings Article | 23 March 2011 Paper

Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization

Koichiro Tsujita, Tadashi Arai, Hiroyuki Ishii, Yuichi Gyoda, Kazuhiro Takahashi, Valery Axelrad, Michael Smayling

Proceedings Volume 7973, 79730D (2011) https://doi.org/10.1117/12.878663

KEYWORDS: Photomasks, Lithography, Optical proximity correction, SRAF, Lithographic illumination, Source mask optimization, Binary data, Double patterning technology, Computer programming, Nanoimprint lithography

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Proceedings Article | 3 April 2010 Paper

16nm with 193nm immersion lithography and double exposure

Valery Axelrad, Michael Smayling

Proceedings Volume 7641, 764109 (2010) https://doi.org/10.1117/12.846677

KEYWORDS: Scanners, Lithography, Lithium, Image quality, Manufacturing, Immersion lithography, Lithographic illumination, Double patterning technology, 193nm lithography, Optical proximity correction

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Proceedings Article | 16 March 2009 Paper

32nm and below logic patterning using optimized illumination and double patterning

Michael Smayling, Valery Axelrad

Proceedings Volume 7274, 72740K (2009) https://doi.org/10.1117/12.814258

KEYWORDS: Logic, Optical lithography, Double patterning technology, Fiber optic illuminators, Lithography, Photomasks, Optical proximity correction, Nanoimprint lithography, Diffusion, Photoresist materials

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Proceedings Article | 28 December 2007 Paper

SoC variability evaluation and reduction

Artur Balasinski, Michael Smayling, Valery Axelrad

Proceedings Volume 6798, 67980I (2007) https://doi.org/10.1117/12.758782

KEYWORDS: Computer aided design, Optical proximity correction, Design for manufacturing, Manufacturing, System on a chip, Field effect transistors, Calibration, Etching, Lithography, Analog electronics

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Proceedings Article | 5 May 2005 Paper

A novel design-process optimization technique based on self-consistent electrical performance evaluation

Valery Axelrad, Andrei Shibkov, Gene Hill, Hung-Jen Lin, Cyrus Tabery, Dan White, Victor Boksha, Randy Thilmany

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600283

KEYWORDS: Device simulation, Transistors, Manufacturing, Design for manufacturing, Light sources, Lithography, Optical proximity correction, Field effect transistors, Process modeling, Critical dimension metrology

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Proceedings Article | 10 July 2003 Paper

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Robert Pack, Valery Axelrad, Andrei Shibkov, Victor Boksha, Judy Huckabay, Rachid Salik, Wolfgang Staud, Ruoping Wang, Warren Grobman

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.499089

KEYWORDS: Lithography, Field effect transistors, Resolution enhancement technologies, Photomasks, Optical proximity correction, Silicon, Transistors, Manufacturing, Binary data, Device simulation

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Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC, alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more cost-effective application of RET.

Proceedings Article | 10 July 2003 Paper

Assessing technology options for 65-nm logic circuits

Dipankar Pramanik, Michel Cote, Kevin Beaudette, Valery Axelrad

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.485256

KEYWORDS: Transistors, Manufacturing, Lithography, Logic, Critical dimension metrology, Device simulation, Resolution enhancement technologies, Photomasks, Oxides, 193nm lithography

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Proceedings Article | 1 August 2002 Paper

Novel procedure for mask disposition using electrical signatures of mask defects

Artur Balasinski, Walter Iandolo, Oindrila Ray, Linard Karklin, Valery Axelrad

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.477005

KEYWORDS: Photomasks, Field effect transistors, Silicon, Inspection, Transistors, Critical dimension metrology, Ions, Defect detection, Particles, Manufacturing

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Proceedings Article | 30 July 2002 Paper

Subwavelength lithography: an impact of photo mask errors on circuit performance

Linard Karklin, Stan Mazor, Devendra Joshi, Artur Balasinski, Valery Axelrad

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474575

KEYWORDS: Photomasks, Lithography, Error analysis, Manufacturing, Monte Carlo methods, Field effect transistors, Optical lithography, Semiconducting wafers, Resolution enhancement technologies, Lithographic illumination

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Proceedings Article | 12 July 2002 Paper

Impact of subwavelength CD tolerance on device performance

Artur Balasinski, Linard Karklin, Valery Axelrad

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475673

KEYWORDS: Tolerancing, Field effect transistors, Optical proximity correction, Silicon, Optical simulations, Resolution enhancement technologies, Transistors, Optical lithography, Semiconducting wafers, Critical dimension metrology

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Proceedings Article | 14 September 2001 Paper

Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data:II. Verification of cell layout based on integration of optical an

Artur Balasinski, Walter Iandolo, Devendra Joshi, Linard Karklin, Valery Axelrad

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435693

KEYWORDS: Metals, Field effect transistors, Critical dimension metrology, Transistors, Integrated optics, Optical proximity correction, Silicon, Cadmium, Optical simulations, Resistance

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Proceedings Article | 7 June 1996 Paper

Efficient computational techniques for aerial imaging simulation

Douglas Bernard, Jiangwei Li, Juan Rey, Khosro Rouz, Valery Axelrad

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240963

KEYWORDS: Photomasks, Computer simulations, Fourier transforms, Cadmium sulfide, Systems modeling, Phase shifts, Airborne remote sensing, Optical lithography, Device simulation, Light sources

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Proceedings Article | 14 September 1994 Paper

Cost and yield estimation in a virtual IC factory

Valery Axelrad, Yuri Granik, Victor Boksha, J. Rollins

Proceedings Volume 2334, (1994) https://doi.org/10.1117/12.186767

KEYWORDS: Data modeling, TCAD, Diffusion, Semiconducting wafers, Manufacturing, Instrument modeling, Process control, Databases, Integrated modeling, Semiconductors

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Proceedings Article | 17 May 1994 Paper

Analysis of microlithography in an open-architecture TCAD system

Valery Axelrad, Victor Boksha, Yuri Granik, Ognjen Milic, Juan Rey, D. Ward, Eduard Tochitsky

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175459

KEYWORDS: Semiconducting wafers, Etching, Semiconductors, TCAD, Oxides, Manufacturing, Optical lithography, Silicon, Monte Carlo methods, Photomasks

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Showing 5 of 23 publications

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