NTD (Negative Tone Developer) technology with application of developer to ArF immersion is one of the technologies that is well known and widely used for enabling better optical image contrast. For critical layer processes, CD (Critical Dimension) control is more difficult with narrow trench and contact hole pattern. Since it is difficult to obtain better CDU (Critical Dimension Uniformity) once mask and resist set have been fixed, new NTD processes are required to improve it. CXMT (Chang Xin Memory Technologies) has been continuously developing manufacturing processes based on new NTD method for narrow pattern DRAM process with TEL™ (Tokyo Electron Limited). In this paper, we discuss our work for CDU improvement with new process on Global, Inter, and Intra shot CDU as well as the optimization results of chemical consumption.
EUV lithography will to be brought into mass production soon. To enhance the yield, improvements in critical dimension (CD) stability, and defectivity still remain of utmost importance. In order to enhance the defectivity ability on contact hole (CH) pattern, continuous work has been executed.1 On 24 nm contact hole half pitch pattern, residue and single-closed hole modes still remain the majority of defects. The main cause of residue defects is that water droplets from the rinse process, in which resist components are absorbed, are dried out on the wafer leaving a remaining residue. While probable causes of single-closed hole are particles included in the coating material or stochastic failures. To reduce the residue defect counts and single-closed hole as caused by in-film particles, optimization of rinse process and material supply system have been carried out. As the result, 97 % of residue defect reduction and 73 % of single-closed hole defect improvement have been achieved as compared with conventional processes. On the other hand, not only coater/developer but also EUV scanner, mask, resist, etc. contribute to the CD variation.1 Global CD uniformity (CDU) is comprised of several components such as wafer-to-wafer CDU, field-to-field one, withinfield one. In this paper, optimization of development processes has been executed to improve field-to-field and within field CDU components. As a result of the optimization, 14 and 6.4 % of field-to-field and within-field CDU improvement have been achieved, respectively.
The key challenge for enablement of a second node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma and e-beam systems, find it difficult to detect the main yield-detracting defects postdevelop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors.
The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield.
This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .
Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. One of the initial layers to be printed with EUV will be contact hole, therefore, we are concentrating on the productivity improvements of that layer.
In our report at SPIE 2017, defect reduction was achieved using the latest rinse technology in the development process and in-film defectivity was improved with material dispense optimization on a 24 nm contact hole (CH) pattern. On the basis of the knowledge acquired from the previous evaluation, improvements have been taken a step further in this next evaluation. As a result, 96% of residue defect reduction and 42% of in -film particle defect reduction has been achieved by further rinse optimization and improvement of dispense system.
For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15% of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the full scaling entitlement of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity and LWR/LER must be improved in terms of patterning performance. Tokyo Electron Limited (TEL™) and IBM Corporation are continuously developing manufacturing quality processes for EUV. In this paper, we review the ongoing progress in coater/developer based processes (coating, developing, baking) that are required to enable EUV patterning.
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