Guest Editors Erik Hosler and Brennan Peterson introduce the Special Section on Next Generation Light Source, Materials, and Metrology/Inspection Equipment.
Quantum computing is one of the grand challenges of the 21st century and promises to transform almost every industry. As quantum computing technology exits the academic research phase into manufacturing, the goal is not to build single, unique qubits, but millions of interconnected, identical qubits capable of performing fully error corrected, general purpose calculations. Photon-based qubits offer a path to such a general-purpose machine by leveraging the mature silicon photonics high-volume manufacturing ecosystem. Creating quantum devices from silicon photonics components requires patterning innovation to bring leading-edge nanolithography to near macroscopic scale, a unique challenge for an industry where the future relies on progressive device shrink.
Quantum computing is the grand challenge of the 21st century and is poised to revolutionizes our daily lives on a nearly unfathomable level. To truly understand the impact, we must first build a universal, fully error corrected machine capable of exploring the application space envisioned by both academic and industry. Numerous pathways have been identified and demonstrated to fabricate single, unique qubits using a myriad of platforms (superconducting, ions, nanoparticles, photons, etc…). However, it is now widely accepted that a truly useful quantum computer will require millions of interconnected, identical qubits to perform fully error corrected, general purpose calculations. To that end, photon-based qubits offer a path to such a general-purpose machine by leveraging the mature silicon photonics high-volume manufacturing ecosystem. Creating quantum devices from silicon photonics components requires patterning innovation to bring leading-edge nanolithography to near macroscopic scale, a unique challenge for an industry where the future relies on progressive device shrink.
Quantum computing is one of the grand challenges of the 21st century and promises to transform almost every industry. As quantum computing technology exits the academic research phase into manufacturing, the goal is not to build single, unique qubits, but millions of interconnected, identical qubits capable of performing fully error corrected, general purpose calculations. Photon-based qubits offer a path to such a general-purpose machine by leveraging the mature silicon photonics high-volume manufacturing ecosystem. Creating quantum devices from silicon photonics components requires patterning innovation to bring leading-edge nanolithography to near macroscopic scale, a unique challenge for an industry where the future relies on progressive device shrink.
Quantum computing has been a long-anticipated emerging computational paradigm to complement and compete with conventional CMOS technologies. The last decade has featured reports of the initial development of using CMOS processing techniques for qubits and the atomistic fabrication of single atom transistors. Will the semiconductor industry embrace this new architype, and if so, how? When quantum devices begin to scale as predicted, will our industry be ready to integrate radically different architectures and device structures? Are there known obstacles not yet addressed that would enable the industry to more readily adopt and benefit from today’s achievements in the laboratory? What are the emerging designs and the potential fundamental challenges that are to be overcome? We have assembled a panel of experts that will share their insights on the state-of-the-art in quantum computing as well as intellectual leaders that will share their vision of the eventual merger of these new technologies with our computing capabilities today, even as lithography is approaching the near-atomic domain. Join us as we discuss the impending critical impact of quantum computing on the semiconductor industry.
Laser-produced plasma (LPP) EUV sources have demonstrated ∼125 W at customer sites, establishing confidence in EUV lithography (EUVL) as a viable manufacturing technology. However, for extension to the 3-nm technology node and beyond, existing scanner/source technology must enable higher-NA imaging systems (requiring increased resist dose and providing half-field exposures) and/or EUV multipatterning (requiring increased wafer throughput proportional to the number of exposure passes). Both development paths will require a substantial increase in EUV source power to maintain the economic viability of the technology, creating an opportunity for free-electron laser (FEL) EUV sources. FEL-based EUV sources offer an economic, high-power/single-source alternative to LPP EUV sources. Should FELs become the preferred next-generation EUV source, the choice of FEL emission architecture will greatly affect its operational stability and overall capability. A near-term industrialized FEL is expected to utilize one of the following three existing emission architectures: (1) self-amplified spontaneous emission, (2) regenerative amplifier, or (3) self-seeding. Model accelerator parameters are put forward to evaluate the impact of emission architecture on FEL output. Then, variations in the parameter space are applied to assess the potential impact to lithography operations, thereby establishing component sensitivity. The operating range of various accelerator components is discussed based on current accelerator performance demonstrated at various scientific user facilities. Finally, comparison of the performance between the model accelerator parameters and the variation in parameter space provides a means to evaluate the potential emission architectures. A scorecard is presented to facilitate this evaluation and provides a framework for future FEL design and enablement for EUVL applications.
Beyond EUV insertion to high-volume manufacturing, the extendibility of the technology is dependent on the cost scaling advantages of high-NA or multi-patterning EUV lithography. Several concerns have been raised regarding the cost and lithographic feasibility of high-NA, including resist performance, productivity, depth of focus, mask infrastructure and field utilization/stitching capability. The intrinsic requirement of half-field exposures for high-NA lithography drives a necessary investigation on reduced field utilization verses stitching performance of the separate half fields. Furthermore, the additional mask for full fields dies will drive additional cost, complexity and overall overhead as compared to EUV NA 0.33 double patterning or other self-aligned technique. Here, the implication to EUV throughput capacity is analyzed within the context of the 7/5/3 nm technology nodes, specifically considering field utilization and scanner productivity as a function of source power and resist dose.
Laser-produced plasma (LPP) EUV sources have demonstrated approximately 125 W at customer sites, establishing confidence in EUV lithography as a viable manufacturing technology. However, beyond the 7 nm technology node existing scanner/source technology must enable higher-NA imaging systems (requiring increased resist dose and providing half-field exposures) and/or EUV multi-patterning (requiring increased wafer throughput proportional to the number of exposure passes. Both development paths will require a substantial increase in EUV source power to maintain the economic viability of the technology, creating an opportunity for free-electron laser (FEL) EUV sources. FEL-based EUV sources offer an economic, high-power/single-source alternative to LPP EUV sources. Should free-electron lasers become the preferred next generation EUV source, the choice of FEL emission architecture will greatly affect its operational stability and overall capability.
A near-term industrialized FEL is expected to utilize one of the following three existing emission architectures: (1) selfamplified spontaneous emission (SASE), (2) regenerative amplification (RAFEL), or (3) self-seeding (SS-FEL). Model accelerator parameters are put forward to evaluate the impact of emission architecture on FEL output. Then, variations in the parameter space are applied to assess the potential impact to lithography operations, thereby establishing component sensitivity. The operating range of various accelerator components is discussed based on current accelerator performance demonstrated at various scientific user facilities. Finally, comparison of the performance between the model accelerator parameters and the variation in parameter space provides a means to evaluate the potential emission architectures. A scorecard is presented to facilitate this evaluation and provide a framework for future FEL design and enablement for EUV lithography applications.
An optimal mix-match control strategy for EUV and 193i scanners is crucial for the insertion of EUV lithography at 7nm technology node. The systematic differences between these exposure systems introduce additional cross-platform mixmatch overlay errors. In this paper, we quantify the EUV specific contributions to mix-match overlay, and explore the effectiveness of higher-order interfield and intrafield corrections on minimizing the on-product mix-match overlay errors. We also analyze the impact of intra-field sampling plans in terms of model accuracy and adequacy in capturing EUV specific intra-field signatures. Our analysis suggests that more intra-field measurements and appropriate placement of the metrology targets within the field are required to achieve the on-product overlay control goals for N7 HVM.
KEYWORDS: Etching, Line edge roughness, Optical lithography, Back end of line, Chemistry, Front end of line, Lithography, Ions, Amorphous silicon, Extreme ultraviolet
Critical back end of line (BEOL) Mx patterning at 7nm technology node and beyond requires sub-36nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the front up approach for Mx grid patterning for most of industry. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed SAQP approach since 10nm node technology, BEOL Mx SAQP is challenging owing to the required usage of significantly lower temperature budgets for film stack deposition. This has an adverse impact on the material properties of the as-deposited films leading to emergence of several challenges for etch including selectivity, uniformity and roughness.
In this presentation we will highlight those unique etch challenges associated with our BEOL Mx SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7nm BEOL Mx, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32nm pitch BEOL SAQP pattern.
At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/self-aligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.
Directed self-assembly (DSA) is a potential patterning solution for future generations of integrated circuits. Its main advantages are high pattern resolution (∼10 nm), high throughput, no requirement of high-resolution mask, and compatibility with standard fab-equipment and processes. The application of Mueller matrix (MM) spectroscopic ellipsometry-based scatterometry to optically characterize DSA patterned contact hole structures fabricated with phase-separated polystyrene-b-polymethylmethacrylate (PS-b-PMMA) is described. A regression-based approach is used to calculate the guide critical dimension (CD), DSA CD, height of the PS column, thicknesses of underlying layers, and contact edge roughness of the post PMMA etch DSA contact hole sample. Scanning electron microscopy and imaging analysis is conducted as a comparative metric for scatterometry. In addition, optical model-based simulations are used to investigate MM elements’ sensitivity to various DSA-based contact hole structures, predict sensitivity to dimensional changes, and its limits to characterize DSA-induced defects, such as hole placement inaccuracy, missing vias, and profile inaccuracy of the PMMA cylinder.
KEYWORDS: Line edge roughness, Silicon, Scatterometry, Data modeling, Optical components, Scanning electron microscopy, Picosecond phenomena, Chemical elements, Line width roughness, Optical properties
Measurement and control of line edge roughness (LER) is one of the most challenging issues facing patterning technology. As the critical dimensions (CDs) of patterned structures decrease, an LER of only a few nanometers negatively impacts device performance. Here, Mueller matrix (MM) spectroscopic ellipsometry-based scatterometry is used to characterize LER in periodic line-space structures in 28-nm pitch Si fin samples fabricated by directed self-assembly patterning. The optical response of the MM elements is influenced by structural parameters like pitch, CDs, height, and side-wall angle, as well as the optical properties of the materials. Evaluation and decoupling MM element response to LER from other structural parameters requires sensitivity analysis using scatterometry models that include LER. Here, an approach is developed that can be used to characterize LER in Si fins by comparing the optical responses generated by systematically varying the grating shape and measurement conditions. Finally, the validity of this approach is established by comparing the results obtained from power spectral density analysis of top down scanning electron microscope images and cross-sectional transmission electron microscope image of the 28-nm pitch Si fins.
Patterning based on directed self-assembly (DSA) of block copolymer (BCP) has been demonstrated to be a cost-effective manufacturing technique for advanced sub-20-nm structures. This paper describes the application of Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry to optically characterize polystyrene-b-polymethylmethacrylate patterns and Si fins fabricated with DSA. A regression-based (inverse-problem) approach is used to calculate the line-width, line-shape, sidewall-angle, and thickness of the DSA structures. In addition, anisotropy and depolarization calculations are used to determine the sensitivity of MMSE to DSA pattern defectivity. As pattern order decreases, the mean squared error value increases, depolarization value increases, and anisotropy value decreases. These specific trends are used in the current work as a method to judge the degree of alignment of the DSA patterns across the wafer.
Measurement and control of line edge roughness (LER) is one of the most challenging issues facing patterning
technology. As the critical dimensions (CD) of patterned structures decrease, LER of only a few nanometers can
negatively impact device performance. Here, Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry is
used to determine LER in periodic line-space structures in 28 nm pitch Si fin samples fabricated by directed selfassembly
(DSA) patterning. The optical response of the Mueller matrix (MM) elements is influenced by structural
parameters like pitch, CD, height, and side-wall angle (SWA), as well as the optical properties of the materials.
Evaluation and decoupling MM element response to LER from other structural parameters requires sensitivity analysis
using simulations of optical models that include LER. Here, an approach is developed that quantifies Si fin LER by
comparing the optical responses generated by systematically varying the grating shape and measurement conditions.
Finally, the validity of this approach is established by comparing the results obtained from top down scanning electron
microscope (SEM) images and cross-sectional TEM image of the 28 nm pitch Si fins.
Simulations of Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry are used to predict sensitivity to dimensional changes and defects in directed self-assembly (DSA) patterned contact hole structures fabricated with phase-separated polystyrene-b-polymethylmethacrylate (PS-b-PMMA) before and after etch. The optical signature of Mueller matrix (MM) elements has a complex dependence on the structure topography and orientation, depolarization, and optical properties of the materials associated with the surface and any underlying layers. Moreover, the symmetry properties associated with MM elements provide an excellent means of measuring and understanding the topography of periodic nanostructures. A forward problem approach to scatterometry or optical model based simulations is used to investigate MMSE sensitivity to various DSA based contact hole structures and its limits to characterize DSA induced defects such as hole placement inaccuracy, missing vias, profile inaccuracy of the PMMA cylinder, and process induced defects such as presence of residual PMMA after etching.
Monte Carlo simulations are used in the semiconductor industry to evaluate variability limits in design rule generation, commonly for interaction between different layers. The variability of the geometry analyzed is determined mainly by the lithography, process and OPC used. Monte Carlo methods for design rule evaluation can provide the requisite level of accuracy, and are suitable for two or more layer interactions because the variations on one can be assumed to be independent of variations on the other(s). The variability parameters and budget utilized in optical Monte Carlo simulations is well-established. With the upcoming implementation of EUV lithography the variability budget will be impacted. EUV has an off-axis illumination angle that complicates the lithography process by causing telecentricity and shadowing errors. Telecentricity errors manifest as a printed feature being shifted relative to the design. The amount the feature is shifted is a function of the pattern density and design. Shadowing is caused by the 3D nature of the mask combined with EUV reflective mask technology. A shadow occurs at feature edges, where the source does not fully illuminate. Telecentricity and shadowing errors, although small at the 10 nm node, will increase in relative size compared to the features printed beyond the 7 nm node. Telecentricity and shadowing errors are complex in nature and can’t be compensated for with a flat bias. These errors unique to EUV are incorporated into Monte Carlo simulations and evaluated against the standard cell design layers. The effect of these variability parameters is evaluated on critical 7 nm node layout clips.
Recent years have seen great strides in the development of extreme ultraviolet (EUV) laser-produced plasma sources. Field deployed EUV exposure tools are now capable of facilitating advanced technology node development. Nevertheless, as the required manufacturing exposure dose scales, EUV sources must follow suit and provide 500- 1000 W to maintain production throughputs. A free-electron laser (FEL) offers a cost effective, single-source alternative for powering an entire EUV lithography program. FEL integration into semiconductor fab architecture will require both unique facility considerations as well as a paradigm shift in lithography operations. Critical accelerator configurations relating to energy recovery, multi-turn acceleration, and operational mode are discussed from engineering/scientific, cost-minimization, and safety perspectives. Furthermore, the individual components of a FEL (electron injector, RF systems, undulator, etc.) are examined with respect to both design and cost, considering existing technology as well as prospective innovations. Finally, FEL development and deployment roadmaps are presented, focusing on manufacturer deployment for the 5 nm or 3 nm technology nodes.[1-3]
Directed self-assembly (DSA) shows considerable promise as a cost-effective manufacturing technique for advanced sub-20 nm patterning. Along with continued progress, the patterning process requires advances in both CD metrology and high-speed characterization of DSA defectivity. This work is a report on the study of Mueller matrix spectroscopic ellipsometry (MMSE) scatterometry measurements of 28 nm pitch DSA line/space patterns consisting of polystyrene-block- polymethylmethacrylate (PS-b-PMMA) block copolymer sample fabricated using a chemical epitaxy process. Generalized ellipsometric data (all 16 Mueller elements) is collected over a spectral range from 245 to 1700 nm for various different pre-pattern pitch/guide strip combinations created by modulating the pre-pattern photoresist CD. Scatterometry is used to evaluate and calculate the CD, line shapes, and thicknesses of the plasma developed PS patterns (PMMA removed). Likewise, spectral comparisons based on anisotropy and depolarization are used to determine the DSA pattern defectivity. CD-SEM metrology and imaging is also conducted as a comparative metric for scatterometry. The sensitivity of MMSE to pre-pattern pitch and pitch multiplication on PS line CD and defectivity is demonstrated. Slight imperfections in the line/space pattern as well as fingerprint like patterns (undirected assembly) can be distinguished from aligned patterns using MMSE scatterometry.
In this paper, we demonstrate the unique advantage of dual-frequency mid-gap capacitively coupled plasma
(m-CCP) in advanced node patterning process with regard to etch rate / depth uniformity and critical dimension
(CD) control in conjunction with wider process window for aspect ratio dependent & microloading effects. Unlike
the non-planar plasma sources, the simple design of the mid-gap CCPs enables both metal and non-metal hard-mask
based patterning, which provides essential flexibility for conventional and DSA patterning. We present data on both,
the conventional multi patterning as well as DSA patterning for trenches / fins and holes. Rigorous CD control and
CDU is shown to be crucial for multi patterning as they lead to undesirable odd-even delta and pitch walking. For
DSA patterning, co-optimized Ne / Vdc of the dual frequency CCPs would be demonstrated to be advantageous for higher organic-to-organic selectivity during co-polymer etching.
Implementation of Directed Self-Assembly (DSA) as a viable lithographic technology for high volume manufacturing
will require significant efforts to co-optimize the DSA process options and constraints with existing work flows. These
work flows include established etch stacks, integration schemes, and design layout principles. The two foremost
patterning schemes for DSA, chemoepitaxy and graphoepitaxy, each have their own advantages and disadvantages.
Chemoepitaxy is well suited for regular repeating patterns, but has challenges when non-periodic design elements are
required. As the line-space polystyrene-block-polymethylmethacrylate chemoepitaxy DSA processes mature,
considerable progress has been made on reducing the density of topological (dislocation and disclination) defects but
little is known about the existence of 3D buried defects and their subsequent pattern transfer to underlayers. In this
paper, we highlight the emergence of a specific type of buried bridging defect within our two 28 nm pitch DSA flows
and summarize our efforts to characterize and eliminate the buried defects using process, materials, and plasma-etch
optimization. We also discuss how the optimization and removal of the buried defects impacts both the process window
and pitch multiplication, facilitates measurement of the pattern roughness rectification, and demonstrate hard-mask open
within a back-end-of-line integration flow. Finally, since graphoepitaxy has intrinsic benefits in terms of design
flexibility when compared to chemoepitaxy, we highlight our initial investigations on implementing high-chi block
copolymer patterning using multiple graphoepitaxy flows to realize sub-20 nm pitch line-space patterns and discuss the
benefits of using high-chi block copolymers for roughness reduction.
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