Mr. Hsiao Lun Chu Profile

Hsiao Lun Chu

at Nanya Technology Corp

SPIE Involvement:

Author

Publications (3)

Proceedings Article | 10 April 2024 Poster + Paper

Optical in die NZO benefit for DRAM manufacturing

Fang-Jyun (June) Yeh, Shang-Hong (Sam) Tsai, Hsiao Lun Chu, Kai Lee, Yun-Ju (York) Yang, Houssam Chouaib, Zhengquan Tan

Proceedings Volume 12955, 129552B (2024) https://doi.org/10.1117/12.3009956

KEYWORDS: Overlay metrology, Semiconducting wafers, Machine learning, Scanning electron microscopy, Education and training, Critical dimension metrology, High volume manufacturing, Metrology, Mueller matrices, Spectroscopic ellipsometry

Read Abstract +

Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Investigation and optimization of STI dry-etch induced overlay through patterned wafer geometry tool

Tsu-Wen Huang, Ying-Cheng Chuang, Hsuan-Jui Huang, Chung-Chang Liu, Hsiao-Lun Chu, Sheng-Yu Chen, Ming-Ju Li, Jun-Eu Tang, Chiou-Shoei Chee, Choon-Wai Chang, Tung-Ying Lee

Proceedings Volume 11611, 1161139 (2021) https://doi.org/10.1117/12.2584589

Read Abstract +

Proceedings Article | 26 March 2019 Paper

Overlay run-to-run control based on device structure measured overlay in DRAM HVM

Hsiao Lun Chu, Foster Huang, Steven Tottewitz, Boris Habets, Patrick Lomtscher, Hsiao-Lin Hsu, Afu Chiu, Rex Liu

Proceedings Volume 10959, 109592P (2019) https://doi.org/10.1117/12.2515203

KEYWORDS: Overlay metrology, Etching, Device simulation, Feedback control, Lithography, Measurement devices, Semiconducting wafers, Control systems, High volume manufacturing, Inspection

Read Abstract +

In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.¹

In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias.

This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.²

This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years