In order to achieve the necessary OPC model accuracy, the requisite number of SEM CD measurements has
exploded with each technology generation. At 65 nm and below, the need for OPC and/or manufacturing
verification models for several process conditions (focus, exposure) further multiplies the number of
measurements required. SEM-contour based OPC model calibration has arisen as a powerful approach to
deliver robust and accurate OPC models since every pixel now adds information for input into the model,
substantially increasing the parameter space coverage. To date however, SEM contours have been used to
supplement the hundreds or thousands of discreet CD measurements to deliver robust and accurate models.
While this is still perhaps the optimum path for high accuracy, there are some cases where OPC test
patterns are not available, and the use of existing circuit patterns is desirable to create an OPC model.
In this work, SEM contours of in-circuit patterns are utilized as the sole data source for OPC model
calibration. The use scenario involves 130 nm technology which was initially qualified for production with
the use of rule-based OPC, but is shown to benefit from model based OPC. In such a case, sub-nanometer
accuracy is not required, and in-circuit features can enable rapid development of sufficiently accurate
models to provide improved process margin in manufacturing.
In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and improved dramatically. These changes are due to the arrival of new verification tools, new companies, new requirements and new awareness by product groups about the necessity of RET verification. Currently, as the 65nm device generation comes into full production and the 45nm generation starts full development, companies now have the tools and experience (i.e., long lists of previous errors to avoid) needed to perform a detailed analysis of what is required for 45nm and 65nm RET verification. In previous work [1] we performed a theoretical analysis of OPC & RET verification requirements for the 65nm and 45nm device generations and drew conclusions for the ideal verification strategy. In this paper, we extend the previous work to include actual observed verification issues and experimental results. We analyze the historical experimental issues with regard to cause, impact and optimum verification detection strategy. The results of this experimental analysis are compared to the theoretical results, with differences and agreement noted. Finally, we use theoretical and experimental results to propose an optimized RET verification strategy to meet the user requirements of 45nm development and the differing requirements of 65nm volume production.
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout
dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must
guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification
methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily
based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these
simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist,
they have often a large number of parameters to fit and suffer from long computing times to execute the simulations.
Simplified resist models are thus needed to enhance run-time computing during simulation.
The objective of this study is to test the predictability of such resist models across the process window. Two
different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The
second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold
to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific
simulations obtained with the two different techniques are compared against experimental results.
Despite the complexity of AAPSM patterning using the complementary PSM approach with respect to OPC correction, mask making, fab logistics etc, the technique still remains a valuable solution for special products where a low CD dispersion printing process is required. For current and next generation process technologies (90-65nm ground rules), the most common alternating mask solution of single trench etch with or without undercut becomes more difficult to manufacture. Especially challenging is the aspect ratio control of quartz etched trenches as a function of density in order to assure the correct phase angle and sidewall for dense and isolated structures over all phase shifted geometries. In order to solve this problem, a modified mask architecture is proposed, called the Transparent Etch Stop Layer (TESL) phase shift mask. In TESL, a transparent (etch stop) layer is deposited on the quartz substrate, followed by the deposition of a quartz layer having a thickness corresponding to the required phase angle for the used wavelength. On top a Chromium layer will be deposited. The patterning of this mask will be quite similar to the single trench variant. The difference is, that now an overetch can be applied for the phase definition resulting from the high etch selectivity of quartz to the etch stop material. The result of this approach should be that we can better control the phase depth and sidewall angle for dense and isolated structures. In this paper we will discuss the results of the printing tests performed using TESL masks especially with respect to litho process window, and we will compare these with the single trench undercut approach. Simulation results are presented with respect to shifter sidewall profile and TESL thickness in order to optimize image imbalance. Throughout the study we will correlate simulations and measurements to the after-MBOPC CD values for the shifter structures. These results will allow us to determine if the TESL AAPSM approach can be a more effective alternative to the single trench undercut approach.
The 65nm and 45nm device generations will be used to manufacture large designs using complex patterning processes in combination with exotic model-based or rule-based RETs’ scenarios. The lithography for these generations will operate in the low k1 regime value resulting in small process window and tight overlay requirements. Therefore, the potential for having yield limiting errors due to RET-process-design interactions is significantly higher than with the 130nm generation.
Additionally, the high cost of reticles and the large number of process layers make it quite important to catch these costly errors.
Optical Rule Checking (ORC) is an effective way to predict failure on wafer shapes. Used in addition to Optical Proximity Correction, it can help to reduce failures affecting yield in manufacturing. Thus, due to the inter-layer complexity of processes and RET, the necessity to check accurately particular areas which could generate costly errors is growing:
Here are some examples: 1) Low metal-contact or metal-via overlaps, 2) Small poly extension past active area, 3) Low overlap between poly and contact layers, and 4) Dual exposure techniques for single layer patterning.
The main difficulty in current implementation of multiple layer RET verification is the trade off between accuracy vs. runtime vs. fault coverage.
In this paper we will demonstrate how based on this trade off we can enhance our final printed results by accurately targeting the most likely failure mechanism on multiple layer processes check in a production environment (90nm node product layout). Finally we will show how ORC in a multiple layer check is going to help detect faults and overlay sensitive areas so as to secure process weakness areas.
We will compare several softwares where such a methodology is applied and attend to propose a post OPC verification strategy to obtain a more robust manufacturing process.
Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows.
For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.
The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.
KEYWORDS: Data modeling, Optical proximity correction, Calibration, Printing, Optical lithography, Scanning electron microscopy, Process modeling, 3D modeling, Lithography, Photomasks
It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.
As lithography continues to increase in difficulty with low k1 factors, and ever-tighter process margins, model-based optical proximity correction (OPC) is being used for the majority of patterning layers. As a result, the engineering effort consumed by the development and calibration of OPC models is continuing to increase at an alarming rate. One of the major focal points of this effort is the increasing emphasis on improving the accuracy of the model-based OPC corrections. One of the major contributors to final OPC accuracy is the quality of the resist model. As a result of these trends, the number of sample points used to calibrate OPC models is increasing rapidly from generation to generation. However, this increase is largely due to an antiquated approach to the construction of these calibration sets, focusing on structure variations. In this study, a new approach to the calibration of a resist model will be proposed based upon the location of calibration structures within the actual resist space over which the resist model is expected to be predictive.
In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance:
1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects.
2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples:
-design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor.
-Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.
As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.
This paper details a study undertaken to revisit defect specifications and maskshop metrology calibration for a mature lithographic process. A programmed array was created containing darkfield and brightfield feature types at various pitches with appropriate OPC sizing. Defects were systematically added to the layout with differing sizes and spacing from the main feature. After exposure with production illumination settings, resist image data was collected and used to determine critical defect sizes. These results are correlated with typical maskshop metrology methods such as AIMS, AVI Photomask Defect Metrology Software (PDMS), and CDSEM. In some cases, it is shown that AIMS data correlates poorly with both defect size and spacing from the feature edge when using illumination settings nominally matched to the exposure tool. Finally, for the particular processes reviewed in this study, the results indicate that the initial reticle defect specifications are often too aggressive for the finalized production lithographic process.
Mask error factor (MEEF) is a commonly used metric in lithography. This parameter gives a good indication of the impact of intra-mask CD variation on the wafer. Unfortunately, MEEF is useless to anticipate the CD variation on the wafer induced by Mask Mean-To-Target variation (MMT). Currently, MMT error is compensated by adjusting the exposure dose. This paper presents the concept of MEV (MEEF Energy-latitude Variation) which is defined by the equation δCDwafer=MEV *δMMT after the dose compensation in a similar way to the MEEF concept. A simple expression for MEV will be presented which shows that the MEV factor is proportional to the variation of the product of EL*MEEF through the population. Using 65nm logic gate level, MEV experimentally shown to be non-zero, and roughly ½ times MEEF factor, which is of course non-negligible in sub 100nm regime. Based on aerial image simulation, pure optical effects are responsible for about 40% of the MEV, which gives a slight predominance of the resist part. Finally, the possibility of reducing the MEV factor by compensating for MTT variation not only by dose but also by illumination settings change is discussed. This will give the basis for an Advanced Process Control (APC) algorithm for the future generations.
In this paper, we present a new technique (Critical Failure ORC or CF-ORC) to check the robustness of the structures created by OPC through the process window. The full methodology is explained and tested on a full chip at the 90- nm node. Improvements compared to standard ORC/MRC techniques will be presented on complex geometries. Finally, examples of concrete failure predictions are given and compared to experimental results.
KEYWORDS: Line edge roughness, Monochromatic aberrations, Transistors, Scanning electron microscopy, 193nm lithography, Cadmium, Optical lithography, Extreme ultraviolet, Etching, Control systems
Tight control of very small transistor gate CDs is one of the most difficult problems in advanced device patterning. Line-edge roughness on these small gate lines has become a serious issue with 193nm lithography and is only expected to worsen with 157nm and EUV lithography. Methods are needed that can minimize line-edge roughness while also enabling the patterning of small gate features. We have analyzed the use of a simple and manufacturable post-develop bake step, a 'hardbake', that controllably reduces both gate resist CDs and to line-edge roughness. Hardbake resist shrinkage is a well-known phenomena from earlier Novolak resist processing, but has not been investigated for chemically amplified resists as much as other CD slimming techniques. Our tests have been performed for different chemically amplified 193nm and EUV-type (essentially reformulated 248nm) resists. The results of our experiments show considerable potential for certain types of resists to provide gate CD control benefits from either roughness reduction or CD slimming.
A new methodology for completely phase-shifting a layout with creating local phase conflicts is proposed for lithographic techniques combining one phase-shifting mask and one binary mask exposure. Critical and non-critical areas of the layout are identified and phase conflicts are avoided by splitting the shifter regions from non-critical areas to non-critical areas without crossing critical areas. The out-of-phase splits of the shifter regions are removed using the binary exposure. Simulation results and experimental data collected for 90 nm technology node show no sign of process latitude loss around the areas where the shifters are split. The overlay latitude is commensurate with 90 nm technology scanner requirements (tool to itself). This approach can also be utilized at the cell library level by creating two copies of each cell with forced phase- shifting boundary conditions. The top and bottom of all the cells have the same phase while the left and right side of each cell have opposite phases, in degrees either 0 - 0 and 180 - 180 or 0 - 180 and 180 - 0. This implementation guarantees conflict-free cell creation and placement.
Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.
Alternating aperture phase shifting mask (AAPSM) technology is finding increased use in the patterning of critical layers due to the enhanced resolution and decreased linewidth variation characteristic of this technique. The potential advantages of AAPSM processes must be weighed against the increased complexity of reticle layout, higher reticle cost, and heightened sensitivity to parameters such as lens aberration. This work details the effect of shifter trench depth on patterning performance for the 100nm node. Data was collected at an exposure wavelength of 193nm using reticles built with deliberate errors in shifter trench depth. Differences in patterning performance observed as a result of these variations are compared with the impact predicted from modeling.
(alpha) -Fluoroalcohols have been proposed as transparent, base-soluble functional groups for use in the design of new 157 nm photoresist polymers. The two most common and easily prepared fluoroisopropanol groups are bis-trifluoromethyl carbinols (hexafluoroalcohol) and methyl-trifluoromethyl carbinols (trifluoroalcohol). This paper describes studies designed to assess the suitability of both of these functionalities as acidic groups. Dissolution rate studies were carried out on polystyrene films that incorporate these groups. The dissolution rates of the sample polymers were compared to that of poly(hydroxystyrene) (PHOST) to provide a reference for the measurements. It was found that the trifluoroalcohol polymers do not exhibit any solubility in basic media, while the hexafluoroalcohol polymers dissolve rapidly relative to PHOST in 0.13N TMAH. Further, it was found that the two fluoroalcohol polymers can be blended to adjust the inherent dissolution rate of the resin and that the hexafluoroalcohol polymer is sensitive to incorporation of classical dissolution inhibitors. The study concludes that hexafluoroalcohol is a promising candidate for incorporation into the design of 157 nm photoresists.
Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.
Finding materials that offer the all of the characteristics required of photoresist matrix resin polymers while trying to maintain a high level of transparency at 157 nm is a daunting challenge. To simplify this task, we have broken the design of these polymers down into subunits, each of which is responsible for a required function in the final material. In addition, we have begun collecting gas-phase VUV spectra of these potential subunits to measure their individual absorbance contributions. Progress on developing materials for each of these subunits are presented along with plans for future studies.
Top surface imaging (TSI) systems based on vapor phase silylation have been investigated for use at a variety of wavelengths. This approach to generating high aspect ratio, high resolution images held great promise particularly for 193 nm and EUV lithography applications. Several 193 nm TSI systems have been described that produce very high resolution (low k factor) images with wide process latitude. However, because of the line edge roughness associated with the final images, TSI systems have fallen from favor. In fact, top surface imaging and line edge roughness have become synonymous in the minds of most. Most of the 193 nm TSI systems are based on poly(p-hydroxystyrene) resins. These polymers have an unfortunate combination of properties that limit their utility in this application. These limiting properties include (1) High optical density (2) Poor silylation contrast (3) Low glass transition temperature of the silylated material. These shortcomings are related to inherent polymer characteristics and are responsible for the pronounced line edge roughness in the poly(p-hydroxystyrene) systems. We have synthesized certain alicyclic polymers that have higher transparency and higher glass transition temperatures. Using these polymers, we have demonstrated the ability to print high resolution features with very smooth sidewalls. This paper will describe the synthesis and characterization of the polymers and their application to top surface imaging at 193 nm. Additionally, it will describe the analysis that was used to tailor the processing and the polymer's physical properties to achieve optimum imaging.
This paper presents the progress we have made toward the development of fully water processable, negative and positive tone I-line resist systems. The negative tone system is based on styrene copolymers bearing pendant ammonium sulfonate groups and vicinal diol functionalities. The salt provides the means of rendering the polymer water soluble. The diol undergoes an acid catalyzed pinacol rearrangement that results in a polarity switch within the exposed polymer film, i.e. a solubility differential. The styrene backbone was chosen to provide dry etch resistance. Positive tone imaging requires two solubility switches. The two solubility switches are based on the reaction between acidic hydroxyl groups in a matrix polymer and vinyl ethers that are introduced as a pendant group of the polymer or as a monomeric cross-linker, i.e. a bisvinyl ether. During the post application bake, the vinyl ether reacts with an acidic hydroxyl group in a thermally activated switch, forming a crosslinked, water insoluble network through acetal linkages. These acid labile crosslink sites are then cleaved by a photochemical switch through the generation of acid, thereby rendering the exposed areas water developable.
This paper reports our work on a series of alicyclic polymer-based photoresist platforms designed for 193 nm lithography. The polymers described here were prepared from derivatives of norbornene and appropriate co-monomers by either free radical or ring opening metathesis polymerization methods. A variety of techniques were explored as a means of enhancing the lithographic, optical, dissolution, and mechanical properties of photoresists formulated from these alicyclic polymers. Recent studies designed to improve the lithographic performance of photoresists formulated with these materials are described.
The interest in imaging materials with improved environmental characteristics has led us to consider imaging formulations coated from and developed in aqueous media, thus avoiding the need for both organic solvents and basic aqueous developer solutions. We have previously reported on the design of several negative-tone resists operating via radiation-induced crosslinking, and while the performance of these negative-tone systems met our basic goals, the resolution that could be achieved was limited due to swelling occurring during development. We now report on various other designs based on polyoxazoline, poly(vinyl alcohol), and methacrylate resins that circumvent this problem with approaches towards both negative- and positive- tone systems.
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