This paper proposes a digital readout integrated circuit (DROIC) for a small pixel MW IRFPA application with a high signal-to-noise ratio (SNR). The storable charge should be substantial enough to maintain a high SNR. A tiny direct injection structure is used for a 7.5 µm pixel pitch. Second, MOSFET and MIM capacitors are employed for integral capacitance to achieve high well capacity. Furthermore, the well capacity issue is addressed by sequentially sharing a bigger capacitor between every two pixels of the arrays. The pixel signal is transferred to the column-level ADC for quantification. DROIC's ADC supports 12 or 13-bit resolution settings to choose from. Following conversion, the digital data of the signal is transferred to the off-chip via multiple output channels. The simulation indicates that the DROIC noise is 1.26 LSBrms at 77K, and the entire well capacity can reach 0.75Me- and 1.5Me- (at 1×2 binning mode), which is advantageous for NETD. The simulation shows that the suggested DROIC is suitable for small-pixel pitch infrared FPAs.
Intra-frame HDR imaging with multiple integration times effectively expands the dynamic range of infrared focal plane array systems at the cost of image quality decreasing due to the loss of spatial resolution. To obtain a positive strategy for improving the intra-frame HDR image quality, a comparison of infrared images obtained from six different integration time arrangements is made. Four image quality assessment metrics, peak-signal-to-noise ratio, structural similarity index measure, natural image quality evaluator and perception-based Image quality evaluator are calculated for comparative analysis. The comparison result shows that the
1 2
3 4
arrangement with four different integration times exhibits the best improvement in image quality and demonstrates that the
1 2
3 4
arrangement has excellent visualization effect in high-quality intra-frame HDR imaging applications.
This paper presents a 14-bit column-parallel two-step compact hybrid ADC for low-power digital IRFPA application, with the area and speed performances compromise. The proposed two-step ADC works in two phases: in the first phase, A 7-bit SAR ADC performs the coarse quantization; in the second phase, a 7-bit SS ADC further performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, and the main clock of fine SS ADC can be reduced to 50MHz at the sampling rate of 238 kS/s. More importantly, by sharing analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are reduced consequently. The proposed two-step ADC is designed in 0.18 μm standard CMOS process. The simulation results show that the proposed two-step ADC has a differential nonlinearity of −0.87/+0.43 LSB and an integral nonlinearity of −0.86/+0.71 LSB. The layout of the proposed ADC can be implemented in the pixel pitch less than 10 μm. The conversion time is 4.2 μs, and the power consumption of each column ADC is only 65 μW with a 3.3V power supply. The simulation results indicate the proposed two-step ADC is suitable for low-power digital readout circuits in the small pixel pitch IRFPA.
With the development of science and technology, image sensors are more and more widely used, such as digital cameras and surveillance cameras. However, due to the physical characteristics of the photodetector, which performance is sensitive to the variation of the operating temperature. Therefore, a digital temperature sensor integrated on the chip is required to measure the operating temperature and assist in correction and compensation. Traditional scheme integrates one temperature sensor on the whole image sensor chip, which can’t reflect the temperature distribution for each pixel. It’s desirable to implement temperature measurement in pixel level for accurate correction, but existing temperature sensor occupying area of hundred μm2, which can’t be input to the pixel of image sensor. In additional, the power consumption of each temperature sensor is μW-level, which will dissipate considerable power for million temperature sensors. In this paper, a pixel-level integrated temperature sensor is proposed. The circuit is composed of only a capacitor and a conventional diode. The readout circuit is similar to that of the active pixel of image sensor, thus the ADC (Analog-to-Digital Converter) and other readout circuits and be multiplexed. The temperature sensor integrated in pixel is designed, which area is only 0.21 μm2. The simulation results show the increased power consumption for 50Hz working pixels don’t exceed 4%. It’s confirmed that the proposed pixel-level integrated temperature sensor can measure the temperature of each pixel and assisting in the accurate correction of image sensor in pixel level.
Region of Interest (ROI) readout is used in readout integrated circuit (ROIC) to improve the frame rate, and reduce the bandwidth for image sensor and infrared Focal Plane Array (IRFPA). The scheme of gray code addressing with the 64×1 minimum size of ROI is widely used. However, the circuit needs to be custom redesigned when the pixel array is changed, which reduces the scalability. The pixel scheme reduces the minimum size of ROI to 1×1. Because of its repeatable circuit design, the scheme has good scalability. But this program occupies the area of pixels, which reduces the dynamic range of image. In this paper, a ROI readout scheme using unit circuit for IRFPA is presented. The minimum size of ROI is reduced to 1×1 in the scheme without occupying the area of pixel. In order to achieve high scalability, reusable circuit named unit circuit is used to control the gating of pixels. The circuit design and simulation results are presented in this paper.
In a digital infrared focal plane array (IRFPA) thermal imager, imaging circuit has requirements of receiving serial data from digital FPA correctly and stably. Conventional data receiving method has disadvantages of low speed, low stability and poor adaptability, which results from clock synchronization difficulty at high data rate and unfixed serial link delay. A novel data receiving method basing on deserializer and sequence detection is proposed. Benefiting from the deserializer, high speed sampling can be implemented, and clock synchronization difficulty is lowered down. With sequence detection, not only the beginning of data packet but also the best sampling point can be correctly determined, even though an uncertain serial link delay exists. The proposed method has been implemented in FPGA achieving a single channel data receiving rate up to 550Mbps. Shaking table testing is completed which fully verifies the high stability and good adaptability of the proposed method.
This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.
This paper presents a two-step ADC architecture for dual band infra-red focal plane array (IRFPA). It has advantages of small pixel area and low power over conventional pixel level ADC while maintaining the characteristic of enhancing well capacity of ROIC. The proposed two-step ADC with 16 bits is designed for middle / long wave (MW/LW) dual band IRFPA: 10-bit pulse frequency modulation (PFM) based pixel level ADC with 6-bit column paralleled Successive Approximation Register (SAR) ADC is employed for LW detector and 6-bit PFM based pixel level ADC with 10-bit column paralleled SAR ADC is employed for MW detector. Layout area of the pixel is 30 μm × 30 μm. The simulation result shows the DNL of the proposed two-step ADC for LW detector and MW detector are 0.6 LSB and 0.9 LSB respectively.
Digital infrared (IR) focal plan array (IRFPA) is one of the most significant characteristic of advanced IR imaging systems, it is implemented by integrating ADCs into the readout integrated circuit (ROIC). Successive Approximation Register (SAR) ADC is popular for column-level ADC architecture since it has low power and high resolution. In this paper a 14-bit RC hybrid SAR ADC with unary capacitor array is proposed, it has better linearity performance area compared with conventional SAR ADC. The proposed SAR ADC introduces resistor ladder for the last 6-bit conversion and it is shared by the whole SAR ADC array, so single SAR ADC’s layout’s length can be reduced, The proposed SAR ADC is designed in 130 nm standard CMOS process, the size of the SAR ADC core is 30 μm × 560 μm. the post simulation result show that its power consumption is 102 μW when the sampling rate is 100 kHz, and the worst DNL is 0.4 LSB when mismatching of 0.2% of capacitor array is introduced. The proposed SAR ADC suits for digital IRFPA applications.
Digital readout integrated circuit (ROIC) has become the development tendency of ROIC for infrared focal plane array (IRFPA) due to its advantages such as improved ability of resisting interference, high readout rate and low readout noise. Compared with traditional analog ROIC, column-parallel analog-to-digital converters (ADCs) are integrated on digital ROIC. Because of the non-ideality of CMOS process, the column nonuniformity of digital ROIC is more obvious than that of analog ROIC due to device mismatch, which will lead to obvious column fixed pattern noise (FPN). In order to reduce column nonuniformity, the main sources of column nonuniformity in digital ROIC are analyzed firstly, including the mismatch between column analog readout channels, as well as ADCs. Then, analytical models have been developed to reveal the relationship between the column FPN and design parameters of digital ROIC. And the numerical computation with CMOS process parameters is implemented. The results show that the column FPN caused by digital ROIC can be reduced to less than 0.1% when the transistor area of tail current source in column analog readout channel is larger than 10μm2 and input transistor area of the first operational amplifier in ADC is larger than 20μm2 . By the help of the proposed mismatch model, column FPN of digital ROIC can be reduced over ten times with optimized design parameters, which provides beneficial guidance for digital ROIC design.
KEYWORDS: Synthetic aperture radar, Quantization, High dynamic range imaging, Signal to noise ratio, Readout integrated circuits, Amplifiers, Image sensors, Imaging systems
This paper presents a two-step ADC architecture for high dynamic range, high sensitivity image sensor. The proposed two-step ADC architecture works in two phases: the coarse quantization phase in each pixel, digital integration technique is applied to increase the well capacity as well as system’s dynamic range, and a capacitive transimpedence amplifier (CTIA) scheme is employed to achieve high sensitivity; The fine quantization phase in the column which reduces the bit width of the pixel-level ADC, pixel-level ADC’s noise and layout area are reduced consequently. The proposed two-step ADC with 18 bits is designed in 0.18 μm standard CMOS process. The optimized assignment for the bit width of pixel-level ADC and column paralleled ADC is applied. The simulation shows the signal to noise ratio (SNR) is 93.5 dB. The dynamic range is 108 dB. The least sensible electrons are 781 e-. The simulation results indicate the proposed twostep ADC is suitable for high dynamic range, high sensitivity image sensor.
A high speed and high dynamic range digital ROIC for infrared FPA detectors is proposed. With using pixel-level ADC and parallel high speed transmission technology, frame rate and dynamic range of the digital ROIC is greatly improved. A 384×288 digital ROIC with pixel parallel charge packet counting ADCs and 4 parallel transmission channels is designed and fabricated using 0.11μm CMOS technology to verify the proposed ROIC architecture. With the proposed ROIC, a high speed high dynamic range infrared FPA detector is achieved with a frame rate of up to1000Hz and a dynamic range of up to 85dB.
In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.
An incremental sigma-delta ADC is designed for column-parallel ADC array in CMOS image sensor. Sigma-delta modulator with single-loop single-bit structure is chosen for power consumption and performance reasons. Second-order modulator is used to reduce conversion time, without stability problem and large area accompanied by higher order sigma-delta modulator. The asymmetric current mirror amplifier used in integrator reduces more than 30% power dissipation. The digital filter and decimator are implemented by counters and adders with significantly reduced chip area and power consumption. A Clock generator is shared by 8 ADCs for trade-off among power, area and clock loading. The ADC array is implemented in a 0.18-μm CMOS technology and clocked at 10 MHz, and the simulated resolution achieves 15-bit with 255 clock cycles. The average power consumption per ADC is 118 μW including clock generator, and the area is only 0.0053 μm2.
CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-μm CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.
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