This article presents results from an algorithm that can automatically quantify critical dimensions in images
from Mask inspection tools with a very high level of accuracy. Using such an algorithm the inspection
systems can be run with much tighter settings, resulting in more false defect detections that can then be
filtered using the algorithm described here. Such a technique could potentially make the inspection system
suitable for inspecting photo-masks beyond its practical limitation.
The ZEISS AIMS™ platform is well established as the industry standard for qualifying the printability of mask
features based on the aerial image. Typically the critical dimension (CD) and intensity at a certain through-focus
range are the parameters which are monitored in order to verify printability or to ensure a successful
repair. This information is essential in determining if a feature will pass printability, but in the case that the
feature does fail, other methods are often required in order to isolate the reason why the failure occurred,
e.g., quartz level deviation from nominal.
Atomic force microscopy (AFM) is typically used to determine physical dimensions such as the quartz etch
depth and sidewall profile. In addition the AFM is a useful tool in monitoring and providing feedback to the
repair engineer, as the depth of the repair is one of the many critical parameters which must be controlled in
order to have a robust repair process.
Carl Zeiss, in collaboration with Photronics-nanoFab, demonstrate the ability to use AIMSTM to provide
quantitative feedback on a given repair process; beyond simple pass/fail of the repair. Using the ZEISS MeRiT®
repair tool as the example, the AIMSTM technique is used in lieu of an AFM to determine if repaired regions are
over-etched or under-etched; and further to predict the amount of MeRiT® recipe change required in order to
bring subsequent repairs to a passing state.
High transmission attenuated phase shift masks (Hi-T PSM) have been successfully applied in volume manufacturing
for certain memory devices. Moreover, numerous studies have shown the potential benefits of Hi-T PSM for specific
lithography applications. In this paper, the potential for extending Hi-T PSM to logic devices, is revisited with an
emphasis on understanding layout, transmission, and manufacturing of Hi-T PSM versus traditional 6% embedded
attenuated phase shift mask (EAPSM). Simulations on various layouts show Hi-T PSM has advantage over EAPSM in
low duty cycle line patterns and high duty cycle space patterns. The overall process window can be enhanced when Hi-
T PSM is combined with optimized optical proximity correction (OPC), sub-resolution assist features (SRAF), and
source illumination. Therefore, Hi-T PSM may be a viable and lower cost alternative to other complex resolution
enhancement technology (RET) approaches. Aerial image measurement system (AIMS) results on test masks, based on
an inverse lithography technology (ILT) generated layout, confirm the simulation results. New advancement in high
transmission blanks also make low topography Hi-T PSM a reality, which can minimize scattering effects in high NA
lithography.
Progressive mask defect problems such as crystal growth or haze are key yield limiters for DUV lithography, especially in 300mm fabs. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality control goal should be to detect any nascent progressive defects before they become yield limiting. So, a high-resolution mask inspection is absolutely needed, but the big question is: “how often do fabs need to re-inspect their masks”? This re-inspection frequency should ideally be the most cost-effective frequency at which there is minimum threat for a yield loss.
Previous work towards finding a cost effective mask re-qualification frequency was done prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years. Other related recent work was done 2004 BACUS conference which is dedicated to DRAM fab data.
In this paper a realistic mask re-qualification frequency model has been developed based on a large volume of data from an advanced logic fab. This work will compliment previous work in this area done with the data from a DRAM fab. Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model.
Progressive mask defect problems such as crystal growth or haze are key yield limiters at DUV lithography, especially in 300mm fabs. With the high energy photons involved in DUV lithography and large wafer size requiring longer continuous exposure of masks, chances of photochemical reaction increases significantly on the masks.
Most of the work published on this subject so far has been focused on defect growth on clear area (on the pattern surface) and on the back-glass of the mask. But there is a new generation of growing defects: crystals that grow on the half-tone (MoSi) film or on the chrome film, on the pattern side of the mask. It is believed that the formation mechanisms and rates are different for these new types of crystals. In light of this instability of masks in volume production, it becomes more important to understand the nature of such defects. The purpose of this investigation is to characterize the nature of these new defect growths and to understand the possible formation mechanisms involved in such problems.
DUV lithography has introduced a progressive mask defect growth problem widely known as crystal growth or haze. Even when incoming mask quality is high, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught early during production in the fabs. In the absence of a solution for the defect’s root cause, the ideal reticle quality control goal should be to detect and monitor any nascent progressive defects before they become yield limiting.
Most of the work published so far has been focused on crystals on clear area (on the pattern surface) and on the back-glass of the mask. But there is a new generation of growing defects: crystals that grow on the half tone (MoSi) film or on the chrome film, on the pattern side of the mask. It is believed that the formation mechanisms and rates are different for these new types of crystals. This work becomes more important with the impact of such defects’ instability on masks in volume production. The purpose of this investigation is to improve manufacturability of PSM’s through haze contamination reduction and to understand the impact and dependency of this contamination on die yield, on reticle lifetime, and on usage patterns.
The ability to transfer designs with high fidelity onto photomasks and then to silicon is an increasingly complex task for advanced technology nodes. For example, the majority of the critical layers for even the 130nm node are patterned by sub-wavelength photolithography; therefore, the numerical aperture, illumination condition, and the resist process must be optimized to achieve the necessary resolution. The reticle, as a bridge between design and process, has become very complex due to the extensive application of resolution enhancement technologies (RETs). As the complexity of RETs increases, the final mask data can be vastly different from the original design due to a series of data manipulations. Optimizing the reticle layout plays the pivotal role in design-for-manufacturability (DFM) considerations.
In this paper, we will discuss how design rules must accommodate the needs of Optical Proximity Correction (OPC) and Phase-shifting Masks (PSM). The final layout on a mask after extensive polygon manipulation must also meet the capability and manufacturability of mask writing, mask inspection, and silicon processing. We will also discuss how the wafer fab's perspective can affect the mask shop. Throughout the discussion, we will demonstrate that the integration at mask level and the collaboration of design, RET, mask shop, and wafer fab are key to DFM success.
With expected implementation of low k1 lithography on 193nm scanners for 65nm node wafer production, high resolution defect inspection will be needed to insure reticle quality and reticle manufacture process monitoring. Reticle cost and reticle defectivity are both increasing with each shrink to the next node. Simultaneously, system on chip (SoC) designs are increasing in which a large area of the exposure field typically contains dummy patterns and other features which are not electrically active. Knowing which defects will electrically impact device yield and performance can improve reticle manufacturing yield and cycle time -- resulting in lower reticle costs. This investigation examines the feasibility of using additional design data layers for die-to-database reticle inspection to determine in real time the relevance of a reticle defect by its location in the device (Smart InspectionTM). The impact to data preparation and inspection throughput is evaluated. The current prototype algorithm is built on the XPA and XPE die-to-database algorithms for chrome-on-glass and EPSM reticles, respectively. The algorithms implement variable sensitivity based on the additional design data regions. During defect review the defects are intelligently binned into the different predetermined design regions. Tests show the new Smart Inspection algorithm provides the capability of using higher than normal sensitivity in critical regions while reducing sensitivity in less critical regions to filter total defect counts and allow for the review of just defects that matter.
Performance characterization of a variable sensitivity Smart Inspection algorithm is discussed in addition to the filtering of the total defect count during review to show the defects that matter to device performance. Using seven critical layer production reticles from a system on chip device we examine the applications of Smart Inspection by layer including active, poly, contact, metal and via layers. Data volume for additional data layers show little impact to inspection data prep time. The total area of the reticle where defects do not matter is as high as 70% on some layers. Review capabilities will be examined for various applications such as reviewing defects in the various regions such as SRAM, dummy pattern, and redundant contact/via specified regions. Lastly, the economics of Smart Inspection will be modeled using the collected knowledge of the applications from the production reticle characterized in this investigation.
Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.
This paper presents a methodology for modeling the space printability at the gate level in 193nm lithography. Spaces are shown to be more susceptible to process variations and lens aberrations than lines are. Experimental Scanning Electron Microscopy (SEM) pictures show that the scum and bridging effects can occur in spaces although all the line critical dimensions (CDs) are on target. A resist imaging model is used to simulate the line CDs through defocus, pitch and size, and the prediction error is within 5nm. However, this model can not reasonably predict space CDs without using variable threshold, which is explained a proposed trajectory dissolution rate model. Based on the dissolution model, a process rule checker is proposed which inspects the peak light intensity in a space and compares it with a given threshold. This condition is verified experimentally.
As the chip making industry gearing up for mass production of 130nm device technology node, Critical Dimension (CD) control becomes ever more important. Among many sources of possible contributions, there is increasing trend that the contributions are being identified for mask making processes itself. For example, at 180nm node, mask contribution to CD control has been 40~45 percent while at 250nm node the contribution was < 20 percent. At 130nm node, it is expected that mask contribution to CD non-uniformity could reach > 60 percent if existing mask making processes are continue to be employed. 60~70 percent of CD non-uniformity contribution from mask is clearly not acceptable. Therefore, we have engaged with our mask suppliers to bring in 50-kV e-beam vector mask pattern generator and dry etch process quickly for critical levels of 130nm device technology node production ramp. In this paper, we will share wafer FAB experiences of quickly implementing the 50-kV vector e-beam pattern generator and dry etch process for 130nm device node ramp. We will be discussing benefits realized from this transition in terms of; mask and wafer pattern fidelity improvements, mask CD linearity Improvements, e-beam writer process resist tone effects, finally and most importantly, impact on the wafer level CD control; Across the Chip Linewidth Variation (ACLV) reductions.
The impact of reticle imperfections on resist critical dimension (CD) variation has greatly increased as design rules shrink to smaller than exposure wavelength. Resolution enhancement techniques, such as optical proximity correction (OPC) and phase-shift mask (PSM), add a great deal of complexity to the mask manufacturing process. Stringent requirements in wafer processing make reticles a crucial factor in CD control. However, making a perfect reticle is a significant challenge for mask manufacturers. In this paper, the strong correlation between reticle and resist CD variation is reported. Multiple sources of hidden CD errors due to imperfect reticles are discussed. Examples include butting errors, grid snapping, OPC model incompatible among reticles with same design rule but with different mask processes, phase-angle and transmission variations in PSM, undetectable reticle defects from reticle inspection, and small reticle defects that are often classified as 'false' defects. Root causes are analyzed and procedures to minimize hidden CD errors are proposed.
Attenuated phase shift masks (PSM) have been widely used in photolithography to enhance resolution and process margin. The advantage of attenuated PSM is further enhanced when it is combined with off-axis illumination (OAI) and optical proximity correction (OPC). This combination results in better performance than when attenuated PSM or OAI is used separately. However, the performance of isolated features is still a limiting factor to improve process margin. One result of such resolution enhancement techniques is conjunction with high numerical aperture imaging systems is an increase in the angles of the light used to form the images. Polarization mismatching among interacting beams becomes worse as the incident angle increases. In this paper we use contact hole patterning as an example to demonstrate how polarization plays a role with different partial coherence factors. PROLITH/3D simulation was used to compare and explain experimental results.
One major limitation of applying attenuated phase shift mask (PSM) is sidelobe printing. The sidelobe is caused by constructive interference of the first order of diffraction maximum from nearby features, plus the electrical fields from semi-transparent materials in the surrounding area. The impact of defocus, lens aberration, and layout design on sidelobe printing are discussed. A detailed comparison between printed wafers and aerial image simulations shows how these factors affect sidelobe printing. Data show tight control on both the third and the fifth order aberrations is critical in PSM application. Since the degree of coherence and the stepper's response to coherence transfer function will significantly affect the performance of PSM, tests on phase shift mask are necessary to qualify a stepper. An alternative approach that uses attenuated rim shifter PSM to prevent sidelobe printing is presented and discussed.
There are an increasing number of issues confronting lithography engineers in modern wafer fabs. Of these problems, yield loss due to reticle defects has received less attention as compared to the shrinking process window of advanced lithographic requirements. Wafer fabs also have concentrated primarily on equipment and people as major sources of yield loss. The requirement of increased focus on reticle defects is examined. The constraints of the current manufacturing capability of mask shops is driving the need for a better method to link the actual lithographic manufacturing process to the reticle defect analysis. This paper will propose a method for integrating the reticle inspection and wafer process as a method for advanced reticle disposition and specification generation. By linking the fab wafer process to the reticle defect inspection a more complete picture of the impact of having reticle defects can be assessed.
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