Dr. Scott W. Jessen Profile

Dr. Scott W. Jessen

RET Technical Manager at Texas Instruments Inc

SPIE Involvement:

Conference Program Committee | Author

Proceedings Article | 20 March 2018 Paper

Improving 130nm node patterning using inverse lithography techniques for an analog process

Can Duan, Scott Jessen, David Ziger, Mizuki Watanabe, Steve Prins, Chi-Chien Ho, Jing Shu

Proceedings Volume 10587, 1058718 (2018) https://doi.org/10.1117/12.2297219

KEYWORDS: Source mask optimization, Lithography, Photomasks, Scanners, Optical proximity correction, Semiconducting wafers, Silicon, Optical lithography

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Proceedings Article | 29 March 2011 Paper

Challenges of SEM-based critical dimension metrology of interconnect

Vladimir Ukraintsev, Scott Jessen, Brian Mikeska, Chris Sallee, Vitali Khvatkov

Proceedings Volume 7971, 797109 (2011) https://doi.org/10.1117/12.882183

KEYWORDS: Critical dimension metrology, Metrology, Scanning electron microscopy, Atomic force microscopy, Photoresist materials, Process control, Cadmium, Semiconducting wafers, Calibration, Optical proximity correction

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Semiconductor technology is advancing below 50 nm critical dimensions bringing unprecedented challenges to process engineering, control and metrology. Traditionally, interconnect metrology is put behind high-priority gate metrology; however, considering metrology, process and yield control challenges this decision is not always justified. Optical scatterometry is working its way to interconnect manufacturing process control, but scanning electron microscopy (SEM) remains the number one critical dimension (CD) metrology for interconnect process engineering and optical proximity correction (OPC) modeling. Recently, several publications have described secondary electron (SE) trapping within narrow high-aspect ratio interconnect structures. In these papers, pre-dosing of the sample helped to extract SE from the bottom of the hole and measure its diameter. Based on current understanding of the phenomenon, one should expect that high-aspect ratio interconnect structures (holes and trenches) with critical dimensions below 100 nm may show signs of SE trapping of various degree. As a result, there may be an uncontrolled effect on SE waveform and, therefore, bias of CDSEM measurement. CD atomic force microscopy (AFM) was employed in this work as a reference metrology for evaluation of uncertainty of trench and hole measurements by CDSEM. As the data indicates, CDSEM bias shows a strong dependence on pitch of periodic interconnect structure starting from drawn CD of 50 nm. CDSEM bias variation for the evaluated set of samples is about 19 nm. A typical OPC sample consists of both photoresist and etched interlayer materials. As the AFM data for photoresist material indicates, the hole diameter changes quite significantly with depth and the hole profile varies from one OPC structure to another. Abe et al. [1] have used a clever way to correlate physical bottom diameter of holes with CDSEM measurements and demonstrated that for their process and dimensions the SEM "top" diameter and physical bottom diameter correlate well. Unfortunately, this conclusion can't be generalized and measurement uncertainty of CDSEM must be evaluated on an individual technology/process basis. A more general approach to improve CDSEM accuracy is necessary which is based upon SI-traceable CDSEM bias measurements, modeling and correction.

Proceedings Article | 3 April 2010 Paper

Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels

Scott Jessen, Steven Prins, James Blatchford, Brian Dillon, Christopher Progler

Proceedings Volume 7641, 76410A (2010) https://doi.org/10.1117/12.848350

KEYWORDS: Metals, Double patterning technology, Photomasks, Etching, Optical lithography, Semiconducting wafers, Lithography, Scanning electron microscopy, Optical proximity correction, Fiber optic illuminators

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Proceedings Article | 13 March 2009 Paper

Exploration of complex metal 2D design rules using inverse lithography

Simon Chang, James Blatchford, Steve Prins, Scott Jessen, Thuc Dam, Guangming Xiao, Linyong Pang, Bob Gleason

Proceedings Volume 7275, 72750D (2009) https://doi.org/10.1117/12.814197

KEYWORDS: Metals, Lithography, Photomasks, Optical lithography, Logic, Raster graphics, Resolution enhancement technologies, Computer simulations, Distributed computing, Visualization

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As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Proceedings Article | 17 March 2008 Paper

32nm design rule evaluation through virtual patterning

Scott Jessen, James Blatchford, Steve Prins, Simon Chang, Yiming Gu, Mark Smith, Dale Legband, Chris Sallee

Proceedings Volume 6925, 692518 (2008) https://doi.org/10.1117/12.772685

KEYWORDS: Optical proximity correction, Semiconducting wafers, SRAF, Lithography, Photomasks, Optical lithography, Lithographic illumination, Image segmentation, Manufacturing, Fiber optic illuminators

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Proceedings Article | 17 March 2008 Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Steve Prins, James Blatchford, Simon Chang, Lewis Flanagin, Scott Jessen, Sean O'Brien, Guangming Xiao, Timothy Lin, Thuc Dam, Bob Gleason

Proceedings Volume 6925, 69250E (2008) https://doi.org/10.1117/12.774581

KEYWORDS: Lithography, SRAF, Photomasks, Logic, Optical proximity correction, Lithographic illumination, Printing, Critical dimension metrology, Design for manufacturing, Model-based design

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Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Proceedings Article | 17 March 2006 Paper

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Scott Jessen, Mark Terry, Mark Mason, Sean O'Brien, Robert Soper, Willie Yarbrough, Thomas Wolf

Proceedings Volume 6156, 615616 (2006) https://doi.org/10.1117/12.660120

KEYWORDS: SRAF, Printing, Optical proximity correction, Lithographic illumination, Fiber optic illuminators, Lithography, Logic devices, Photomasks, Metals, Logic

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Proceedings Article | 15 March 2006 Paper

Across wafer focus mapping and its applications in advanced technology nodes

Gary Zhang, Stephen DeMoor, Scott Jessen, Qizhi He, Winston Yan, Sopa Chevacharoenkul, Venugopal Vellanki, Patrick Reynolds, Joe Ganeshan, Jan Hauschild, Marco Pieters

Proceedings Volume 6154, 61540N (2006) https://doi.org/10.1117/12.657752

KEYWORDS: Semiconducting wafers, Sensors, Chemical mechanical planarization, Scanners, Back end of line, Monochromatic aberrations, Calibration, Process control, Front end of line, Etching

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The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact the device yield. A technique based on the Phase-Shift Focus Monitor (PSFM) is developed to measure realistic across-wafer focus errors on materials processed in actual production flows. With this technique, we are able to extract detailed across-wafer focus performance at critical pattern levels from the front end of line (FEOL) all the way through the back end of line (BEOL). Typically, more than 8,000 data points are measured across a wafer, and the data are decomposed into an intra-field focus map, which captures the across chip focus variation (ACFV), and an inter-field focus map, which describes the across wafer focus variation (AWFV). ACFV and AWFV are then analyzed to understand various components in the overall focus error, including; across slit lens image field, reticle shape and dynamic scan components, local wafer flatness, wafer processing effect, pattern density, and edge die abnormality. The intra-field ACFV lens component is compared with TI's ScatterLith and ASML's FOCAL techniques. Results are consistent with the predictions based on the on-board lens aberration data. Inter-field AWFV is the most interesting, due to lack of detailed understanding of the process impact on scanner focus and leveling. PSFM data is used to characterize the effect of wafer processing such as etch, deposition, and CMP on across wafer focus control. Comparison and correlation of PSFM focus mapping with the wafer height and residual moving average (MA) maps generated by the scanner's optical leveling sensors shows a good match in general. Process induced focus errors are clearly observed on wafers of significant film stack variation and/or pattern density variation. Implications on total focus control and depth of focus (DOF) requirements for 65nm mass production are discussed in this paper using a quantitative pattern yield model. The same technique can be extended to immersion lithography.

Proceedings Article | 5 May 2005 Paper

Design rule considerations for 65-nm node contact using off axis illumination

Scott Jessen, Mark Mason, Sean O'Brien, Mark Terry, Robert Soper, Thomas Wolf

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600005

KEYWORDS: SRAF, Printing, Photomasks, Optical proximity correction, Manufacturing, Lithography, Solids, Logic, Image resolution, Model-based design

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Proceedings Article | 17 December 2003 Paper

Mask challenges and capability development for the 65-nm device technology node: the first status report

Won Kim, Christopher Aquino, Mark Eickhoff, Phillip Lim, Nobuhiko Fukuhara, Scott Jessen, Yasutaka Kikuchi, Junichi Tanzawa

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518205

KEYWORDS: SRAF, Photomasks, Inspection, Resolution enhancement technologies, Printing, Solids, Lithography, Mask making, Semiconducting wafers, Critical dimension metrology

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Proceedings Article | 30 July 2002 Paper

Integration using KrF and ArF resist materials in a full via firstdual-damascene process scheme with CVD OSG low-k dielectric

Scott Jessen, K. Steiner, Thomas Wolf, William Josephson, S. Lytle, Mitsuru Sato, Chung Lee, Ming Fan

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474632

KEYWORDS: Dielectrics, Lithography, Polymers, Etching, Photoresist processing, Chemical vapor deposition, Optical lithography, Photoresist materials, Semiconductors, Phase transfer function

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Proceedings Article | 1 December 1997 Paper

Low-energy photophysics of phenylene-based strapped copolymers

Arthur Epstein, N. Piskun, Ilia Lebedenko, Scott Jessen, Terry Gustafson, Dian-Kui Fu, Timothy Swager

Proceedings Volume 3145, (1997) https://doi.org/10.1117/12.279284

KEYWORDS: Absorption, Polymers, Luminescence, Excitons, Absorbance, Solids, Quantum efficiency, Polarons, Chlorine, Picosecond phenomena

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Proceedings Article | 1 December 1997 Paper

Long-lived polarons and triplet excitons in ladder-type poly(p-phenylenes) and poly(p-phenylene ethynylenes)

Jonathan Partee, Joseph Shinar, Wilhelm Graupner, Guenther Leising, Scott Jessen, Arthur Epstein, Yi Ding, Thomas Barton

Proceedings Volume 3145, (1997) https://doi.org/10.1117/12.295527

KEYWORDS: Polarons, Excitons, Magnetism, Personal protective equipment, Polymers, Microwave radiation, Luminescence, Resonance enhancement, Signal processing, Solids

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Proceedings Article | 15 September 1995 Paper

Five-layered symmetrically configured ac light-emitting (SCALE) devices and their three-layered variations: use of gold as an electron and hole injection electrode

Yunzheng Wang, Darren Gebler, James Blatchford, Scott Jessen, L. Lin, Terry Gustafson, Hsing-Lin Wang, Y. Park, Timothy Swager, Alan MacDiarmid, Arthur Epstein

Proceedings Volume 2528, (1995) https://doi.org/10.1117/12.219560

KEYWORDS: Polymers, Electrodes, Gold, Aluminum, Electroluminescence, Light emitting diodes, Metals, Interfaces, Polarons, Absorption

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Showing 5 of 14 publications

Conference Committee Involvement (16)

Advances in Patterning Materials and Processes XLII

24 February 2025 | San Jose, California, United States

Advances in Patterning Materials and Processes XLI

26 February 2024 | San Jose, California, United States

Advances in Patterning Materials and Processes XL

27 February 2023 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXIX

25 April 2022 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXVIII

22 February 2021 | Online Only, California, United States

Advances in Patterning Materials and Processes XXXVII

24 February 2020 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXVI

25 February 2019 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXV

27 February 2018 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXIV

28 February 2017 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXIII

29 February 2016 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXII

24 February 2015 | San Jose, California, United States

Advances in Patterning Materials and Processes XXXI

24 February 2014 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXX

25 February 2013 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXIX

13 February 2012 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXVIII

28 February 2011 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXVII

22 February 2010 | San Jose, California, United States

Showing 5 of 16 Conference Committees

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