Mr. Seung Weon Paek Profile

Seung Weon Paek

at SAMSUNG Electronics Co Ltd

SPIE Involvement:

Author

Publications (16)

Proceedings Article | 27 April 2023 Paper

Paper

AI-guided reliability diagnosis for 5,7nm automotive process

Dongin Kim, Hyung Joo Lee, Sanghyun Choi, Seungpyo Hong, Seungjae Lee, Doohwan Kwak, Srividya Jayaram, Seungwon Paek, Minho Kwon, Yeongdo Kim, Hyobe Jung, Ivan Kissiov, Melody Tao, Andres Torres, Nathan Greeneltch, Ho Lee

Proceedings Volume 12496, 124963J (2023) https://doi.org/10.1117/12.2662880

KEYWORDS: Reliability, Semiconducting wafers, Data modeling, Manufacturing, Fabrication, Semiconductors, Industry, High volume manufacturing, Model-based design, Metrology

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Proceedings Article | 4 April 2019 Presentation + Paper

Presentation + Paper

A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Jaehwan Kim, Sangah Lee, Byungchul Shin, J. Jeon, Jin Kim, B. M. Kim, Jae-Hyun Kang, Seungweon Paek, Piyush Pathak, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 10962, 1096204 (2019) https://doi.org/10.1117/12.2514896

KEYWORDS: Computer aided design, Metals, Resolution enhancement technologies, Optical lithography, CMOS technology, Extreme ultraviolet, Extreme ultraviolet lithography, Lithography, Double patterning technology, Manufacturing

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Proceedings Article | 20 March 2019 Paper

Paper

Machine learning to improve accuracy of fast lithographic hotspot detection

NamJae Kim, Kiheung Park, Jiwon Oh, Sangwoo Jung, Sangah Lee, Jae-hyun Kang, Seung Weon Paek, Kareem Madkour, Wael ElManhawy, Aliaa Kabeel, Ahmed ElGhoroury, Marwa Shafee, Asmaa Rabie, Joe Kwan

Proceedings Volume 10962, 1096216 (2019) https://doi.org/10.1117/12.2515139

KEYWORDS: Machine learning, Data modeling, Lithography, Neural networks, Manufacturing, Computer simulations, Design for manufacturability, Design for manufacturing, Feature extraction, Electronics

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Proceedings Article | 18 March 2015 Paper

Paper

High coverage of litho hotspot detection by weak pattern scoring

Jinho Park, NamJae Kim, Jae-hyun Kang, Seung Weon Paek, Steve Kwon, Marwah Shafee, Kareem Madkour, Wael ElManhawy, Joe Kwan, Jean-Marie Brunet

Proceedings Volume 9427, 942703 (2015) https://doi.org/10.1117/12.2087473

KEYWORDS: Phase modulation, Lithography, Image classification, Library classification systems, Visualization, Process modeling, Design for manufacturing, Manufacturing, Yield improvement, Land mines

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Achieving lithographic printability at advanced nodes (14nm and beyond) can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. Early identifying of yield-limiter hotspots is essential for both foundries and designers to significantly improve process maturity. A real challenge is to scan the design space to identify hotspots, and decide the proper course of action regarding each hotspot. Building a scored pattern library with real candidates for hotspots for both foundries and designers is of great value. Foundries are looking for the most used patterns to optimize their technology for and identify patterns that should be forbidden, while designers are looking for the patterns that are sensitive to their neighboring context to perform lithographic simulation with their context to decide if they are hotspots or not.[1] In this paper we propose a framework to data mine designs to obtain set of representative patterns of each design, our aim is to sample the designs at locations that can be potential yield limiting. Though our aim is to keep the total number of patterns as small as possible to limit the complexity, still the designer is free to generate layouts results in several million of patterns that define the whole design space. In order to handle the large number of patterns that represent the design building block constructs, we need to prioritize the patterns according to their importance. The proposed pattern classification methodology depends on giving scores to each pattern according to the severity of hotspots they cause, the probability of their presence in the design and the likelihood of causing a hotspot. The paper also shows how the scoring scheme helps foundries to optimize their master pattern libraries and priorities their efforts in 14nm technology and beyond. Moreover, the paper demonstrates how the hotspot scoring helps in improving the runtime of lithographic simulation verification by identifying which patterns need to be optimized to correctly describe candidate hotspots, so that only potential problematic patterns are simulated.

Proceedings Article | 15 March 2012 Open Access

Open Access

Paper

Yield enhancement with DFM

Seung Weon Paek, Jae Hyun Kang, Naya Ha, Byung-Moo Kim, Dae-Hyun Jang, Junsu Jeon, DaeWook Kim, Kun Young Chung, Sung-eun Yu, Joo Hyun Park, SangMin Bae, DongSup Song, WooYoung Noh, YoungDuck Kim, HyunSeok Song, HungBok Choi, Kee Sup Kim, Kyu-Myung Choi, Woonhyuk Choi, JoongWon Jeon, JinWoo Lee, Ki-Su Kim, SeongHo Park, No-Young Chung, KangDuck Lee, YoungKi Hong, BongSeok Kim

Proceedings Volume 8327, 832704 (2012) https://doi.org/10.1117/12.920029

KEYWORDS: Design for manufacturing, Silicon, Polishing, Optical proximity correction, Back end of line, Metals, Failure analysis, Yield improvement, Logic, Manufacturing

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Proceedings Article | 15 March 2012 Paper

Paper

In-design process hotspot repair using pattern matching

Daehyun Jang, Naya Ha, Junsu Jeon, Jae-Hyun Kang, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ya-Chieh Lai, Philippe Hurat, Wilbur Luo

Proceedings Volume 8327, 83270S (2012) https://doi.org/10.1117/12.916199

KEYWORDS: Silicon, Manufacturing, Lithography, Failure analysis, Data processing, Chemical mechanical planarization, Semiconducting wafers, Design for manufacturability, Tolerancing, Optical lithography

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Proceedings Article | 15 March 2012 Paper

Paper

Thickness-aware LFD for the hotspot detection induced by topology

Jae-Hyun Kang, Naya Ha, Joo-Hyun Park, Byung-Moo Kim, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ahmed Mohy, Shady Abdelwahed, Mohamed Imam

Proceedings Volume 8327, 83270P (2012) https://doi.org/10.1117/12.917998

KEYWORDS: Semiconducting wafers, Metals, Process modeling, Image processing, Design for manufacturing, Chemical mechanical planarization, Optical proximity correction, 3D modeling, Photovoltaics, Scanning electron microscopy

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Proceedings Article | 5 April 2011 Paper

Paper

In-design DFM CMP flow for block level simulation using 32nm CMP model

Naya Ha, Jinwoo Lee, S. W. Paek, Kee Sup Kim, Kuang Han Chen, Aaron Gower-Hall, Tamba Gbondo-Tugbawa, Philippe Hurat

Proceedings Volume 7974, 79740W (2011) https://doi.org/10.1117/12.880899

KEYWORDS: Chemical mechanical planarization, Metals, Copper, System on a chip, Design for manufacturing, Manufacturing, Dielectrics, Polishing, Device simulation, Logic

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Proceedings Article | 4 April 2011 Paper

Paper

A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation

Mark Simmons, Jae-Hyun Kang, Youngkeun Kim, Joung Il Park, Seung weon Paek, Kee-sup Kim

Proceedings Volume 7974, 79740M (2011) https://doi.org/10.1117/12.881596

KEYWORDS: Computer aided design, Lithography, Semiconducting wafers, Device simulation, Design for manufacturing, Data modeling, Semiconductors, Manufacturing, Pattern recognition, Visualization

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In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

Proceedings Article | 13 March 2009 Paper

Paper

Enhanced layout optimization of sub-45nm standard: memory cells and its effects

Seung Weon Paek, Dae Hyun Jang, Joo Hyun Park, Naya Ha, Byung-Moo Kim, Hyo Sig Won, Kyu-Myung Choi, Kuang-Kuo Lin, Simon Klaver, Shobhit Malik, Michiel Oostindie, Frank Driessen

Proceedings Volume 7275, 72751M (2009) https://doi.org/10.1117/12.815413

KEYWORDS: Design for manufacturing, Semiconducting wafers, Yield improvement, Manufacturing, Laser induced breakdown spectroscopy, Standards development, Tolerancing, Optimization (mathematics), Optical proximity correction, Silicon

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Proceedings Article | 4 March 2008 Paper

Paper

System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator

Mark Simmons, Jean-Marie Brunet, Seung-Weon Paek, Y. K. Kim

Proceedings Volume 6925, 69250X (2008) https://doi.org/10.1117/12.771821

KEYWORDS: Optical proximity correction, Product engineering, Process modeling, Computer aided design, Resolution enhancement technologies, Semiconducting wafers, Data modeling, Manufacturing, Error analysis, Calibration

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Proceedings Article | 14 September 2001 Paper

Paper

Feasibility study on the ArF attenuated phase-shift mask for 100-nm node lithography

Sang-Sool Koo, Sang-Jin Kim, Seung-Weon Paek, Chang-Nam Ahn, Young-Mog Ham, Ki-Soo Shin

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435776

KEYWORDS: Lithography, Photomasks, Electroluminescence, Optical lithography, Critical dimension metrology, Semiconducting wafers, Printing, Photoresist processing, Scanning electron microscopy, Photomicroscopy

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Proceedings Article | 5 September 2001 Paper

Paper

Impact of ArF attenuated PSM using multishifter layer (TiN/Si3N4) for next-generation lithography

Kyung-Han Nam, Lee-Ju Kim, Hyoung-Sup Jeong, Sang Lee, In-Soo Lee, Cheol Shin, Hong-Seok Kim, L. Dieu, Seung-Weon Paek, Sang-Sool Koo, Sang-Man Bae, Young-Mog Ham, Ki-Soo Shin

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438396

KEYWORDS: Photomasks, Lithography, Mask making, Semiconducting wafers, Phase shifts, Dry etching, Scanning electron microscopy, Electroluminescence, 193nm lithography, Photoresist processing

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Proceedings Article | 22 January 2001 Paper

Paper

Potentialities of sub-100-nm optical lithography of alternating and phase-edge phase-shift mask for ArF lithography

Sang-Sool Koo, Hee-Bom Kim, Hyoung-Soon Yune, Jee-Suk Hong, Seung-Weon Paek, Tae-Seung Eom, Chang-Nam Ahn, Young-Mog Ham, Ki-Ho Baik, Kyu-Yong Lee, Lee-Ju Kim, Hong-Seok Kim

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410711

KEYWORDS: Lithography, Photomasks, Critical dimension metrology, Phase shifts, Electroluminescence, Optical lithography, Chromium, Etching, Mask making, Scanning electron microscopy

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Proceedings Article | 19 July 2000 Paper

Paper

Mask critical dimension error on optical lithography

Tae-Seung Eom, Sang-Sool Koo, Seung-Weon Paek, Hee-Bom Kim, Chang-Nam Ahn, Ki-Ho Baik

Proceedings Volume 4066, (2000) https://doi.org/10.1117/12.392047

KEYWORDS: Photomasks, Optical lithography, Diffusion, Critical dimension metrology, Lithography, Transmittance, Semiconducting wafers, Lithographic illumination, Phase shifts, Image processing

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Proceedings Article | 5 July 2000 Paper

Paper

Validation of repair process for DUV attenuated phase-shift mask

Seung-Weon Paek, Hee-Bom Kim, Chang-Nam Ahn, Young-Mo Koo, Ki-Ho Baik

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.389051

KEYWORDS: Photomasks, Semiconducting wafers, Deep ultraviolet, Lithography, Data modeling, Control systems, Binary data, Tolerancing, Opacity, Reliability

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Showing 5 of 16 publications

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