Dr. Yuansheng Ma Profile

Dr. Yuansheng Ma

Distinguished Product Engineer

SPIE Involvement:

Editorial Board Member: Journal of Micro/Nanopatterning, Materials, and Metrology | Author

Publications (38)

Proceedings Article | 13 November 2024 Presentation

Presentation

Monotonic machine learning for lithography retargeting layer generation by leveraging contour-based metrology

Yuansheng Ma, Haizhou Yin, Le Hong, Xuefeng Zeng, Xiaomei Li, Hongming Zhang, Jeongmi Lee, Xiaoyuan Qi, Neal Lafferty, Germain Fenger, George Lippincott, Jiechang Hou, Abdulrazaq Adams, Xima Zhang, Yuyang Sun, Danping Peng, Renyang Meng, Werner Gillijns

Proceedings Volume 13216, 132161V (2024) https://doi.org/10.1117/12.3034720

KEYWORDS: Etching, Machine learning, Metrology, Modeling, Semiconductor manufacturing, Data modeling, Contour extraction, Simulations, Scanning electron microscopy, Image processing

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Proceedings Article | 10 April 2024 Presentation

Presentation

Machine learning (ML) based SEM contour extraction accelerated by GPU for etch modeling application

Yuansheng Ma, Xuefeng Zeng, Yunxiang Wang, Haizhou Yin, Xiaoyuan Qi, Shibing Wang, Le Hong

Proceedings Volume PC12958, (2024) https://doi.org/10.1117/12.3012442

KEYWORDS: Scanning electron microscopy, Contour extraction, Modeling, Etching, Machine learning, Metrology, Data modeling, Contour modeling, Semiconductors, Industry

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Proceedings Article | 10 April 2024 Presentation

Presentation

Layout simulation for directed self-assembly with chemo-epitaxy methodology

Shibing Wang, Yixiao Zhang, Jiechang Hou, Yuansheng Ma, Daman Khaira, Germain Fenger, Yuyang Sun, Bassem Hamieh, Boaz Alperson, Durairaj Baskaran, Md Rahman, Jerome Wandell, Youngjun Her

Proceedings Volume 12954, 129540W (2024) https://doi.org/10.1117/12.3010510

KEYWORDS: Directed self assembly, Stochastic processes, Optical lithography, Line edge roughness, Extreme ultraviolet, Atomic layer deposition, Semiconductors, Product engineering, Polymers, Personal protective equipment

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Proceedings Article | 30 April 2023 Presentation

Presentation

A ML based OPC model pattern down-selection method with mask and wafer contours

Xuefeng Zeng, Yuansheng Ma, Yixiao Zhang, Yuyang Sun

Proceedings Volume PC12499, PC1249905 (2023) https://doi.org/10.1117/12.2662778

KEYWORDS: Semiconducting wafers, Photomasks, Optical proximity correction, Scanning electron microscopy, Calibration, Optical simulations, Machine learning, Wafer-level optics, Semiconductors, Semiconductor manufacturing

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Proceedings Article | 30 April 2023 Presentation

Presentation

Extending design technology co-optimization from technology launch to HVM

Le Hong, Fan Jiang, Yuansheng Ma, Srividya Jayaram, Joe Kwan, Haizhou Yin, Xiaoyuan Qi, Junjiang Lei

Proceedings Volume 12495, 124950G (2023) https://doi.org/10.1117/12.2658652

KEYWORDS: Manufacturing, Optical proximity correction, Failure analysis, Design for manufacturability, Analytics, Semiconductors, Semiconducting wafers, Metrology, Inspection, Design for manufacturing

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Proceedings Article | 28 April 2023 Paper

Paper

EUV full-chip curvilinear mask options for logic via and metal patterning

Neal Lafferty, Sagar Saxena, Keisuke Mizuuchi, Yuansheng Ma, Xima Zhang, Pat LaCour, Alexander Tritchkov, Farah Kmiec, John Sturtevant

Proceedings Volume 12495, 124950K (2023) https://doi.org/10.1117/12.2647882

KEYWORDS: SRAF, Optical proximity correction, Machine learning, Lithography, Simulations

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Proceedings Article | 13 June 2022 Presentation

Presentation

Fast full-chip curvilinear ILT mask generation with machine learning technology

Yuangsheng Ma, Rui Wu, Junjiang Lei, Le Hong, Keisuke Mizuuchi, Fan Jiang, Alexander Tritchkov, Yuyang Sun

Proceedings Volume 12052, 120520V (2022) https://doi.org/10.1117/12.2619416

KEYWORDS: Photomasks, Machine learning, Optical proximity correction, Lithography, Semiconducting wafers, Fluctuations and noise, Visualization, Vestigial sideband modulation, Vector spaces, Product engineering

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As an advanced form of optical proximity correction (OPC), Inverse Lithography Technology (ILT) calculates the desired shapes on a photomask in free-form curvilinear types. It has become one of the key computational lithography solutions for advanced technology nodes, which may enable the most challenging features in IC designs and produce mask output that results in better process latitude and CD control on wafer than the one using conventional OPC [1]. Although curvilinear ILT technology has taken root in limited cases such as in hot spot repairment and in memory [2], it still experiences difficulties to be adopted as a full-chip solution due to its long computation time and consistency issues. In this paper, we will leverage Siemens pxOPC and introduce a fast full-chip curvilinear ILT mask generation flow with Mentor Graphics Calibre SONR, a Machine Learning (ML) method [3]. Siemens pxOPC TM is pixel-based optimization product designed to maximize lithography quality in terms of EPE, Common Process Window, ILS/NILS, MEEF, etc. It uses image gradient to indicate the mask movement and minimize the gradient magnitude to achieve the final mask. Calibre SONR is a product built upon Mentor’s Machine Learning Platform (MLP) combining multiple related applications under one license. It uses feature vectors which are shown to correlate well with design and fab printing behavior. SONR implements fuzzy Pattern Matching (PM) in feature vector space, which is different from traditional PM (either exact or fuzzy) in topological space. For the case of pattern reduction, traditional fuzzy PM selects patterns which are close geometrically to a reference pattern, while SONR make further pattern reduction without loss in pattern coverage since different topological patterns may share similar feature vectors. In this paper, we build a flow to use SONR to analyze patterns across the full chip and make corresponding selections for the final pxOPC solutions. With comparable wafer performance, our preliminary results show that the flow may exceed the existing best practice in terms of runtime reduction, enhanced full-chip consistency, and robust full-chip run. Figure 1 shows that the run time is improved by 60%. This paper is organized as follows. pxOPC is introduced in Section I. Our proposed SONR pattern reduction flow is described in Section II, followed by the fast full-chip curvilinear mask generation flow in Section III. Then Section IV provides simulation results and discussion in Section IV. Section V conclusions the paper. Keyword: Curvilinear, ILT, pxOPC, mask, machine learning, pattern selection, layout reduction REFERENCES [1] Le Hong, Fan Jiang, Alexander Tritchkov, James Word, Dan Zhang, “Inverse Lithography Recipe Optimization Using Genetic Algorithm”, SPIE 105871H (2018). [2] Linyong (Leo) Pang, P. Jeffrey Ungar, Ali Bouaricha , Lu Sha, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Ryan Pearman, and Aki Fujimura "TrueMask ILT MWCO: full-chip curvilinear ILT in a day and full mask multi-beam and VSB writing in 12 hrs for 193i", Proc. SPIE 11327, Optical Microlithography XXXIII, 113270K (31 March 2020) [3] Yuansheng Ma, Le Hong, James Word, Fan Jiang, Vlad Liubich, Liang Cao, Srividya Jayaram, Doohwan Kwak, YoungChang Kim, Germain Fenger, Ananthan Raghunathan, Joerg Mellmann, “Reduction of Systematic Defects through Machine Learning from Design to Fab “, SPIE 11329-9 (2020)

Proceedings Article | 8 November 2021 Presentation + Paper

Presentation + Paper

Optimizing curvilinear ILT recipe development with machine learning based pattern selection

Yuansheng Ma, Rui Wu, Junjiang Lei, Keisuke Mizuuchi, Alexander Tritchkov, Fan Jiang, Dingyi Hong, Rehab Ali, Le Hong, Yuyang Sun

Proceedings Volume 11855, 118550T (2021) https://doi.org/10.1117/12.2601918

KEYWORDS: Photomasks, Machine learning, Optical proximity correction, Data modeling, Lithography, Calibration, Semiconducting wafers, Printing, Fuzzy logic, Vector spaces

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Proceedings Article | 23 March 2020 Presentation + Paper

Presentation + Paper

Reduction of systematic defects with machine learning from design to fab

Yuansheng Ma, Le Hong, James Word, Fan Jiang, Vlad Liubich, Liang Cao, Srividya Jayaram, Doohwan Kwak, YoungChang Kim, Germain Fenger, Ananthan Raghunathan, Joerg Mellmann

Proceedings Volume 11329, 1132909 (2020) https://doi.org/10.1117/12.2551703

KEYWORDS: Machine learning, Optical proximity correction, Photomasks, Etching, Data modeling, Process modeling, Neural networks, Semiconducting wafers, Inspection

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Proceedings Article | 20 March 2019 Presentation + Paper

Presentation + Paper

Machine learning based wafer defect detection

Yuansheng Ma, Feng Wang, Qian Xie, Le Hong, Joerg Mellmann, Yuyang Sun, Shao Wen Gao, Sonal Singh, Panneerselvam Venkatachalam, James Word

Proceedings Volume 10962, 1096208 (2019) https://doi.org/10.1117/12.2513232

KEYWORDS: Data modeling, Machine learning, Semiconducting wafers, Defect detection, Statistical modeling, Optics manufacturing, Optical proximity correction, Wafer-level optics, Feature extraction, High volume manufacturing

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Proceedings Article | 28 March 2018 Presentation + Paper

Presentation + Paper

Combinational optical rule check on hotspot detection

Alexander Wei, Shaowen Gao, Yuansheng Ma, Shumay Shang, Yuyang Sun, Rui Wu, Lianghong Yin, Hongxin Zhang

Proceedings Volume 10588, 105880K (2018) https://doi.org/10.1117/12.2297425

KEYWORDS: Optical proximity correction, Failure analysis, Semiconducting wafers, Calibration, Data modeling, Photomasks, Inspection, Optics manufacturing, Bridges, Finite element methods

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SPIE Journal Paper | 23 March 2018

Model-based guiding pattern synthesis for robust assembly of contact layers using directed self-assembly

Joydeep Mitra, Andres Torres, Yuansheng Ma, David Pan

JM3, Vol. 17, Issue 01, 013508, (March 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.1.013508

KEYWORDS: Directed self assembly, Connectors, Global Positioning System, Curium, Model-based design, Detection and tracking algorithms, Calibration, Monte Carlo methods, Data modeling, Failure analysis

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Proceedings Article | 20 March 2018 Presentation + Paper

Presentation + Paper

Model-assisted template extraction SRAF application to contact holes patterns in high-end flash memory device fabrication

Ahmed Seoud, Juhwan Kim, Yuansheng Ma, Srividya Jayaram, Le Hong, Gyu-Yeol Chae, Jeong-Woo Lee, Dae-Jin Park, Hyoung-Soon Yune, Se-Young Oh, Chan-Ha Park

Proceedings Volume 10587, 105870L (2018) https://doi.org/10.1117/12.2297659

KEYWORDS: SRAF, Lithography, Optical proximity correction, Optical lithography

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Proceedings Article | 30 March 2017 Presentation + Paper

Presentation + Paper

Design technology co-optimization (DTCO) study on self-aligned-via (SAV) with Lamella DSA for sub-7 nm technology

Yuansheng Ma, Jongwook Kye, Gurdaman Khaira, Le Hong, James Word, Yuyang Sun, Joydeep Mitra, J. Andres Torres, Germain Fenger, Harry Levinson

Proceedings Volume 10148, 101480B (2017) https://doi.org/10.1117/12.2258056

KEYWORDS: Optical lithography, Optical proximity correction, Directed self assembly, Resolution enhancement technologies, Etching, Monte Carlo methods, Photomasks, Manufacturing, Metals, Logic, Visualization, Error analysis, Solids

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Proceedings Article | 21 March 2017 Presentation + Paper

Presentation + Paper

Overview and development of EDA tools for integration of DSA into patterning solutions

J. Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova, Dehia Ait-Ferhat

Proceedings Volume 10144, 101440E (2017) https://doi.org/10.1117/12.2264178

KEYWORDS: Electronic design automation, Photomasks, Polymers, Optical lithography, Design for manufacturing, Lithography, Epitaxy, Inspection, Directed self assembly, Manufacturing, Systems modeling, Visualization, Data modeling

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Directed Self-Assembly is the method by which a self-assembly polymer is forced to follow a desired geometry defined or influenced by a guiding pattern. Such guiding pattern uses surface potentials, confinement or both to achieve polymer configurations that result in circuit-relevant topologies, which can be patterned onto a substrate.

Chemo, and grapho epitaxy of lines and space structures are now routinely inspected at full wafer level to understand the defectivity limits of the materials and their maximum resolution. In the same manner, there is a deeper understanding about the formation of cylinders using grapho-epitaxy processes. Academia has also contributed by developing methods that help reduce the number of masks in advanced nodes by “combining” DSA-compatible groups, thus reducing the total cost of the process.

From the point of view of EDA, new tools are required when a technology is adopted, and most technologies are adopted when they show a clear cost-benefit over alternative techniques. In addition, years of EDA development have led to the creation of very flexible toolkits that permit rapid prototyping and evaluation of new process alternatives. With the development of high-chi materials, and by moving away of the well characterized PS-PMMA systems, as well as novel integrations in the substrates that work in tandem with diblock copolymer systems, it is necessary to assess any new requirements that may or may not need custom tools to support such processes.

Hybrid DSA processes (which contain both chemo and grapho elements), are currently being investigated as possible contenders for sub-5nm process techniques. Because such processes permit the re-distribution of discontinuities in the regular arrays between the substrate and a cut operation, they have the potential to extend the number of applications for DSA.

This paper illustrates the reason as to why some DSA processes can be supported by existing rules and technology, while other processes require the development of highly customized correction tools and models. It also illustrates how developing DSA cannot be done in isolation, and it requires the full collaboration of EDA, Material’s suppliers, Manufacturing equipment, Metrology, and electronic manufacturers.

Proceedings Article | 21 March 2017 Paper

Paper

Model-based guiding pattern synthesis for on-target and robust assembly of via and contact layers using DSA

Joydeep Mitra, Andres Torres, Yuansheng Ma, David Pan

Proceedings Volume 10144, 1014414 (2017) https://doi.org/10.1117/12.2257314

KEYWORDS: Calibration, Printing, Resolution enhancement technologies, Monte Carlo methods, Lithography, Model-based design, Optimization (mathematics), Detection and tracking algorithms, Directed self assembly, Connectors, Photomasks, Optical lithography

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SPIE Journal Paper | 29 September 2016

Directed self-assembly compliant flow with immersion lithography: from material to design and patterning

Yuansheng Ma, Yan Wang, James Word, Junjiang Lei, Joydeep Mitra, Juan Andres Torres, Le Hong, Germain Fenger, Daman Khaira, Moshe Preil, Jongwook Kye, Harry Levinson

JM3, Vol. 15, Issue 03, 031610, (September 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.3.031610

KEYWORDS: Directed self assembly, Lens design, Optical lithography, Immersion lithography, Photomasks, Neck, Lithography, Critical dimension metrology, Visualization, Optical proximity correction

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Proceedings Article | 22 March 2016 Paper

Paper

Directed Self Assembly (DSA) compliant flow with immersion lithography: from material to design and patterning

Yuansheng Ma, Yan Wang, James Word, Junjiang Lei, Joydeep Mitra, J. Andres Torres, Le Hong, Germain Fenger, Daman Khaira, Moshe Preil, Lei Yuan, Jongwook Kye, Harry Levinson

Proceedings Volume 9777, 97770N (2016) https://doi.org/10.1117/12.2219505

KEYWORDS: Optical lithography, Semiconducting wafers, Lithography, Directed self assembly, Immersion lithography, Extreme ultraviolet, Optical resolution, Neck, Modulation, Photomasks, Lens design, Ions, Neodymium, Visualization, Code division multiplexing

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SPIE Journal Paper | 11 September 2015

Directed self-assembly graphoepitaxy template generation with immersion lithography

Yuansheng Ma, Junjiang Lei, J. Andres-Torres, Le Hong, James Word, Germain Fenger, Alexander Tritchkov, George Lippincott, Rachit Gupta, Neal Lafferty, Yuan He, Joost Bekaert, Geert Vanderberghe

JM3, Vol. 14, Issue 03, 031216, (September 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.3.031216

KEYWORDS: Dysprosium, Photomasks, Immersion lithography, Source mask optimization, Optical proximity correction, Printing, Optical lithography, Visualization, Lens design, Directed self assembly

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Proceedings Article | 19 March 2015 Paper

Paper

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

Yuansheng Ma, Junjiang Lei, J. Torres, Le Hong, James Word, Germain Fenger, Alexander Tritchkov, George Lippincott, Rachit Gupta, Neal Lafferty, Yuan He, Joost Bekaert, Geert Vanderberghe

Proceedings Volume 9423, 942306 (2015) https://doi.org/10.1117/12.2085850

KEYWORDS: Photomasks, Optical proximity correction, Printing, Source mask optimization, Optical lithography, Neodymium, Visualization, Transmission electron microscopy, Dysprosium, Directed self assembly

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Proceedings Article | 18 March 2015 Paper

Paper

Incorporating DSA in multipatterning semiconductor manufacturing technologies

Yasmine Badr, J. Torres, Yuansheng Ma, Joydeep Mitra, Puneet Gupta

Proceedings Volume 9427, 94270P (2015) https://doi.org/10.1117/12.2084776

KEYWORDS: Photomasks, Lithography, Electron beam lithography, Optical lithography, Directed self assembly, Manufacturing, Semiconductor manufacturing, Visualization, Annealing, Optics manufacturing

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Proceedings Article | 16 March 2015 Paper

Paper

Directed self assembly on resist-limited guiding patterns for hole grapho-epitaxy: Can DSA help lower EUV's source power requirements?

J. Torres, Fan Jiang, Yuansheng Ma, Joerg Mellman, Kafai Lai, Ananthan Raghunathan, Yongan Xu, Chi-Chun Liu, Cheng Chi

Proceedings Volume 9422, 94220W (2015) https://doi.org/10.1117/12.2085959

KEYWORDS: Line edge roughness, Extreme ultraviolet, Polymethylmethacrylate, Picosecond phenomena, Lithography, Polymers, Directed self assembly, Monte Carlo methods, Visualization, Extreme ultraviolet lithography

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Proceedings Article | 17 October 2014 Paper

Paper

Compact model experimental validation for grapho-epitaxy hole processes and its impact in mask making tolerances

Germain Fenger, J. Andres Torres, Yuansheng Ma, Yuri Granik, Polina Krasnova, Antoine Fouquet, Jérôme Belledent, Ahmed Gharbi, Raluca Tiron

Proceedings Volume 9231, 92310Q (2014) https://doi.org/10.1117/12.2065840

KEYWORDS: Data modeling, Scanning electron microscopy, Photomasks, Optical proximity correction, Semiconducting wafers, Calibration, Neodymium, Mask making, Tolerancing, Directed self assembly

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Proceedings Article | 17 October 2014 Paper

Paper

Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications

Yuansheng Ma, J. Andres Torres, Germain Fenger, Yuri Granik, Julien Ryckaert, Geert Vanderberghe, Joost Bekaert, James Word

Proceedings Volume 9231, 92310T (2014) https://doi.org/10.1117/12.2065508

KEYWORDS: Optical lithography, Photomasks, Metals, Modulation, Lithography, Optical proximity correction, Monte Carlo methods, Printing, Phase shift keying, Directed self assembly

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Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

Proceedings Article | 8 October 2014 Paper

Paper

Calibration and application of a DSA Compact model for graphoepitaxy hole processes using contour-based metrology

Germain Fenger, Andrew Burbine, J. Andres Torres, Yuansheng Ma, Yuri Granik, Polina Krasnova, Geert Vandenberghe, Roel Gronheid, Joost Bekaert

Proceedings Volume 9235, 92351X (2014) https://doi.org/10.1117/12.2069188

KEYWORDS: Data modeling, Calibration, Photomasks, Monte Carlo methods, Double patterning technology, Ions, Cements, Metrology, Neodymium, Directed self assembly

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Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.

Proceedings Article | 28 March 2014 Paper

Paper

Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes

J. Andres Torres, Kyohei Sakajiri, David Fryer, Yuri Granik, Yuansheng Ma, Polina Krasnova, Germain Fenger, Seiji Nagahara, Shinichiro Kawakami, Benjamen Rathsack, Gurdaman Khaira, Juan de Pablo, Julien Ryckaert

Proceedings Volume 9053, 90530R (2014) https://doi.org/10.1117/12.2045328

KEYWORDS: Monte Carlo methods, Manufacturing, Lithography, Metals, Photomasks, Optical lithography, Directed self assembly, Visualization, Polymers, Design for manufacturability

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Proceedings Article | 15 March 2012 Paper

Paper

Self-aligned double patterning (SADP) compliant design flow

Yuangsheng Ma, Jason Sweis, Hidekazu Yoshida, Yan Wang, Jongwook Kye, Harry Levinson

Proceedings Volume 8327, 832706 (2012) https://doi.org/10.1117/12.917775

KEYWORDS: Double patterning technology, Photomasks, Optical lithography, Silicon, Critical dimension metrology, Standards development, Electronic design automation, Metals, Capacitance, Extreme ultraviolet

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Proceedings Article | 5 April 2011 Paper

Paper

DPT restricted design rules for advanced logic applications

Yunfei Deng, Yuangsheng Ma, Hidekazu Yoshida, Jongwook Kye, Harry Levinson, Jason Sweis, Tamer Coskun, Vishnu Kamat

Proceedings Volume 7973, 79730H (2011) https://doi.org/10.1117/12.879793

KEYWORDS: Double patterning technology, Optical lithography, Lithography, Metals, Resolution enhancement technologies, Source mask optimization, Manufacturing, Logic, Immersion lithography, Extreme ultraviolet lithography

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Proceedings Article | 4 April 2011 Paper

Paper

Double patterning compliant logic design

Yuangsheng Ma, Jason Sweis, Chris Bencher, Yunfei Deng, Huixiong Dai, Hidekazu Yoshida, Bimal Gisuthan, Jongwook Kye, Harry Levinson

Proceedings Volume 7974, 79740D (2011) https://doi.org/10.1117/12.879846

KEYWORDS: Double patterning technology, Semiconducting wafers, Logic, Optical lithography, Etching, Metals, Back end of line, Neodymium, Standards development, Scanning electron microscopy

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SPIE Journal Paper | 1 October 2010

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations

Yongchan Ban, Yuangsheng Ma, Harry Levinson, David Pan

JM3, Vol. 9, Issue 04, 041211, (October 2010) https://doi.org/10.1117/12.10.1117/1.3504697

KEYWORDS: Resistance, Lithography, TCAD, Manufacturing, Design for manufacturability, Line edge roughness, Instrument modeling, Optical lithography, Edge roughness, Critical dimension metrology

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Proceedings Article | 3 April 2010 Paper

Paper

Decomposition strategies for self-aligned double patterning

Yuansheng Ma, Jason Sweis, Chris Bencher, Huixiong Dai, Yongmei Chen, Jason Cain, Yunfei Deng, Jongwook Kye, Harry Levinson

Proceedings Volume 7641, 76410T (2010) https://doi.org/10.1117/12.848387

KEYWORDS: Photomasks, Optical lithography, Etching, Dielectrics, Double patterning technology, Image processing, Logic, Scanning electron microscopy, Back end of line, Metals

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Proceedings Article | 3 April 2010 Paper

Paper

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell

Yongchan Ban, Yuansheng Ma, Harry Levinson, Yunfei Deng, Jongwook Kye, David Pan

Proceedings Volume 7641, 76410D (2010) https://doi.org/10.1117/12.846654

KEYWORDS: Resistance, Lithography, TCAD, Optical lithography, Line edge roughness, Critical dimension metrology, Manufacturing, Device simulation, Edge roughness, Optical proximity correction

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Proceedings Article | 11 March 2010 Paper

Paper

Considerations in source-mask optimization for logic applications

Yunfei Deng, Yi Zou, Kenji Yoshimoto, Yuansheng Ma, Cyrus Tabery, Jongwook Kye, Luigi Capodieci, Harry Levinson

Proceedings Volume 7640, 76401J (2010) https://doi.org/10.1117/12.848865

KEYWORDS: Source mask optimization, Lithography, Photomasks, Printing, Optimization (mathematics), Logic, Photoresist processing, Process modeling, 3D modeling, Optical lithography

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Proceedings Article | 4 March 2010 Paper

Paper

Spacer defined double patterning for sub-72 nm pitch logic technology

Ryoung-Han Kim, Erin Mclellan, Yunpeng Yin, John Arnold, Sivananda Kanakasabapathy, Sanjay Mehta, Yuansheng Ma, Martin Burkhardt, Jason Cain, Greg McIntyre, Matthew Colburn, Harry Levinson

Proceedings Volume 7640, 76400F (2010) https://doi.org/10.1117/12.846698

KEYWORDS: Double patterning technology, Critical dimension metrology, Image processing, Photoresist processing, Lithography, Photomasks, Etching, Optical lithography, Scanning electron microscopy, Logic

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Proceedings Article | 16 March 2009 Paper

Paper

Overcoming the challenges of 22-nm node patterning through litho-design co-optimization

Martin Burkhardt, J. C. Arnold, Z. Baum, S. Burns, J. Chang, J. Chen, J. Cho, V. Dai, Y. Deng, S. Halle, G. Han, S. Holmes, D. Horak, S. Kanakasabapathy, R. H. Kim, A. Klatchko, C. S. Koay, A. Krasnoperova, Y. Ma, E. McLellan, K. Petrillo, S. Schmitz, C. Tabery, Y. Yin, L. Zhuang, Y. Zou, J. Kye, V. Paruchuri, S. Mansfield, C. Spence, M. Colburn

Proceedings Volume 7274, 727404 (2009) https://doi.org/10.1117/12.814433

KEYWORDS: Etching, Lithography, Printing, Optical lithography, Double patterning technology, Resolution enhancement technologies, Logic, Metals, Photomasks, Tolerancing

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Proceedings Article | 1 April 2008 Paper

Paper

Proposal for determining exposure latitude requirements

Harry Levinson, Yuansheng Ma, Marcel Koenig, Bruno La Fontaine, Rolf Seltmann

Proceedings Volume 6924, 69241J (2008) https://doi.org/10.1117/12.772711

KEYWORDS: Critical dimension metrology, Line edge roughness, Photomasks, Semiconducting wafers, Image processing, Diffusion, Lithography, Light scattering, Optical lithography, Photoresist processing

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Proceedings Article | 11 April 2007 Paper

Paper

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

Thomas Wallow, Alden Acheta, Yuansheng Ma, Adam Pawloski, Scott Bell, Brandon Ward, Cyrus Tabery, Bruno La Fontaine, Ryoung-han Kim, Sarah McGowan, Harry Levinson

Proceedings Volume 6519, 651919 (2007) https://doi.org/10.1117/12.712319

KEYWORDS: Line edge roughness, Etching, Photoresist materials, Spatial frequencies, Lithography, Smoothing, Image processing, Critical dimension metrology, Semiconducting wafers, Photoresist processing

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Proceedings Article | 5 April 2007 Paper

Paper

Line edge roughness impact on critical dimension variation

Yuansheng Ma, Harry Levinson, Thomas Wallow

Proceedings Volume 6518, 651824 (2007) https://doi.org/10.1117/12.712388

KEYWORDS: Critical dimension metrology, Line edge roughness, Fractal analysis, Etching, Monte Carlo methods, Scanning electron microscopy, Transistors, Line width roughness, Fourier transforms, Spatial frequencies

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Showing 5 of 38 publications

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